add more

.gitignore

@@ -2,3 +2,4 @@ icarusTest
 top.asc
 top.bin
 wave.vcd
+pnr.log

Makefile

@@ -5,13 +5,14 @@ pcf_file = io.pcf
 build:
 	yosys -qp "synth_ice40 -json $(filename).json" $(filename).v
 	nextpnr-ice40 -q\
+		-l pnr.log \
 		--up5k \
 		--package sg48 \
 		--json $(filename).json \
 		--pcf $(pcf_file) \
 		--asc $(filename).asc
 	icepack $(filename).asc $(filename).bin
-
+#	head -n -434 pnr.log | tail -18
 #prog: #for sram
 	#iceprog -S $(filename).bin
 

Readme.md

+iverilog -o icarusTest top.v && vvp icarusTest

alu.v

@@ -5,8 +5,11 @@ module alu(
     input enAdd,
     input enSub,
     input clr,
+    input wrFlags,
     input [15:0] busIn,
-    output [15:0] busOut
+    output [15:0] busOut,
+    output carryFlag,
+    output zeroFlag
 );
 
   wire [15:0] aVal;
@@ -43,5 +46,23 @@ module alu(
     .currentLo(bValLo)
   );
 
+  reg zeroFlagReg = 0;
+  reg carryFlagReg = 0;
+
+  assign zeroFlag = zeroFlagReg;
+  assign carryFlag = carryFlagReg;
+
+  always @ (posedge clr) begin
+    zeroFlagReg <= 0;
+    carryFlagReg <= 0;
+  end
+
+  always @ (posedge clk) begin
+      if (wrFlags) begin
+          zeroFlagReg <= (busIn == 0) ? 1'b1 : 1'b0;
+          carryFlagReg <= (aVal + bVal > 15'b111111111111111) ? 1'b1 : 1'b0;
+      end
+  end
+
   assign busOut = enAdd ? aVal + bVal : (enSub ? aVal - bVal : 15'b0);
 endmodule
\ No newline at end of file

ram.v

@@ -36,7 +36,7 @@ module ram(
     end
   end
 
-  reg [7:0] ramMemory [0:1024];
+  reg [7:0] ramMemory [0:10];
 
 
 

top.v

@@ -6,8 +6,21 @@
 `include "alu.v"
 
 
-module top(input [3:0] SW, output LED_R, output LED_G, output LED_B, output TX, input P3_10);
+module top(input [3:0] SW, output LED_R, output LED_G, output LED_B, input P3_10, input clk,
 
+  output P1_1, output P1_2, output P1_3, output P1_4, output P1_9, output P1_10, output P1_11, output P1_12);
+  reg clr = 1;
+
+
+  always @(negedge sClk)begin
+    clr <= 0;
+  end
+
+
+  reg sClk = 0;
+  `ifndef SYNTHESIS
+  always #1 sClk = ~sClk;
+  `endif
 
   wire [15:0] bus_in_1;
   wire [15:0] bus_in_3;
@@ -19,45 +32,57 @@ module top(input [3:0] SW, output LED_R, output LED_G, output LED_B, output TX,
   wire [15:0] bus_out;
   assign bus_out = bus_in_1 | bus_in_2 | bus_in_3 | bus_in_4 | bus_in_5 | bus_in_6;
 
-  reg [22:0] clock_div;
-  reg sClk;
-  wire hlt;
 
-  wire [7:0] tmpout;
+  assign LED_R = sClk;
+
+
+  reg [18:0] clock_div;
+  // reg sClk;
+  reg hlt = 0;
+
+  reg tmp =0;
+  reg one =1;
+
+  assign P1_12 = bus_out[0]; //LSB
+  assign P1_1 = bus_out[1];
+  assign P1_11 = bus_out[2];
+  assign P1_2 = bus_out[3];
+  assign P1_10 = bus_out[4];
+  assign P1_3 = bus_out[5];
+  assign P1_9 = bus_out[6];
+  assign P1_4 = bus_out[7]; //MSB
+
+  always @(posedge clk)
+  begin
+
+    // Slow clock gen
+    clock_div <= clock_div + 1;
+    if(clock_div == 0 & ~hlt) begin
+      sClk <= ~sClk;
+    end
+
+
+
+  end
+
 
   // reg [7:0] tmpbyte;
   // assign tmpbyte = (clock_div[7:0] & 8'b00001111) | 8'b00110000 ;
 
   // dff #(.WIDTH(8)) ff1(.d(tmpbyte), .q(tmpout), .clr(clr), .clk(P3_10));
 
-  reg wrZlo = 0;
-  reg wrZhi = 0;
-  reg enZlo = 0;
-  reg enZhi = 0;
-
-  register zReg (.clk(clk),.clr(clr),.in(bus_out),.out(bus_in_1),.wrHi(wrZhi),.wrLo(wrZlo),.enHi(enZhi),.enLo(enZlo));
 
 
-  reg wrMarHi = 0;
-  reg wrMarLo = 0;
-  reg wrRam = 0;
-  reg enRam = 0;
-  ram workingRam(.clk(clk), .clr(clr), .busIn(bus_out), .busOut(bus_in_3), .wrMarHi(wrMarHi), .wrMarLo(wrMarLo), .wrRam(wrRam), .enRam(enRam));
+  register zReg (.clk(sClk),.clr(clr),.in(bus_out),.out(bus_in_1),.wrHi(wrZhi),.wrLo(wrZlo),.enHi(enZhi),.enLo(enZlo));
 
-  reg incPc=0;
-  reg enPc=0;
-  reg wrPc=0;
-  pc programCounter(.inc(incPc), .clk(clk), .enPc(enPc), .wrPc(wrPc), .clr(clr), .busIn(bus_out), .busOut(bus_in_4) );
+  ram workingRam(.clk(sClk), .clr(clr), .busIn(bus_out), .busOut(bus_in_3), .wrMarHi(wrMarHi), .wrMarLo(wrMarLo), .wrRam(wrRam), .enRam(enRam));
 
-  reg clr = 0;
-  reg clk = 0;
-  always #1 clk = ~clk;
+  pc programCounter(.inc(incPc), .clk(sClk), .enPc(enPc), .wrPc(wrPc), .clr(clr), .busIn(bus_out), .busOut(bus_in_4) );
 
+  reg [5:0] stateCounter = 0;
 
-  reg [2:0] stateCounter = 0;
-  reg rstState = 0;
 
-  always @ (negedge clk or posedge clr) begin
+  always @ (negedge sClk or posedge clr) begin
       if (clr) begin
           stateCounter <= 0;
       end else begin
@@ -65,24 +90,60 @@ module top(input [3:0] SW, output LED_R, output LED_G, output LED_B, output TX,
       end
   end
 
-  always @ (posedge clk) begin
-      if (rstState) begin
-          stateCounter <= 0;
-      end
-  end
+  // always @ (posedge clk) begin
+  //     if (rstState) begin
+  //         stateCounter <= 0;
+  //     end
+  // end
 
-  wire [7:0]controlWord = {stateCounter,currentOp[5:0]};
+  wire carryFlag;
+  wire zeroFlag;
+  wire [14:0]controlWord = {currentOp[6:0],stateCounter,zeroFlag,carryFlag};
+  // wire [7:0]controlWord = {stateCounter};
   wire [15:0]controlLines;
 
-  reg [15:0] controlMemory [0:255];
+  reg [15:0] controlMemory [0:32767];
 
   assign controlLines = controlMemory[controlWord];
 
+  wire wrA = controlLines[0];
+  wire wrB = controlLines[1];
+  wire enSub = controlLines[2];
+  wire enAdd = controlLines[3];
+  wire wrZlo = controlLines[4];
+  wire wrZhi = controlLines[5];
+  wire enZlo = controlLines[6];
+  wire enZhi = controlLines[7];
+  wire incPc = controlLines[8];
+  wire enPc = controlLines[9];
+  wire wrPc = controlLines[10];
+  wire rstState = controlLines[11];
+  wire wrMarHi = controlLines[12];
+  wire wrMarLo = controlLines[13];
+  wire wrRam = controlLines[14];
+  wire enRam = controlLines[15];
+  reg wrFlags = 0;
+  // reg wrA = 0;
+  // reg wrB = 0;
+  // reg enSub = 0;
+  // reg enAdd = 1;
+  // reg wrZlo = 0;
+  // reg wrZhi = 0;
+  // reg enZlo = 0;
+  // reg enZhi = 0;
+  // reg incPc = 1;
+  // reg enPc = 0;
+  // reg wrPc = 0;
+  // reg rstState = 0;
+  // reg wrMarHi = 0;
+  // reg wrMarLo = 0;
+  // reg wrRam = 0;
+  // reg enRam = 0;
 
   reg wrInst = 0;
   reg enInst = 0;
   wire [7:0]currentOp;
-  register instReg (.clk(clk),
+  register instReg (.clk(sClk),
                     .clr(clr),
                     .in(bus_out),
                     .out(bus_in_5),
@@ -94,29 +155,37 @@ module top(input [3:0] SW, output LED_R, output LED_G, output LED_B, output TX,
                     );
 
 
-  reg wrA = 0;
-  reg wrB = 0;
-  reg enSub = 0;
-  reg enAdd = 0;
+
 
   alu alu(
-      .clk(clk),
+      .clk(sClk),
       .wrA(wrA),
       .wrB(wrB),
       .enAdd(enAdd),
       .enSub(enSub),
       .clr(clr),
       .busIn(bus_out),
-      .busOut(bus_in_6)
+      .busOut(bus_in_6),
+      .wrFlags(wrFlags),
+      .carryFlag(carryFlag),
+      .zeroFlag(zeroFlag)
   );
 
   initial begin
     $readmemh("control.mem", controlMemory);
+
     $dumpfile("wave.vcd");
     $dumpvars;
 
-    #2 clr = 1;
-    #2 clr = 0;
+    `ifndef SYNTHESIS
+    #300 $finish;
+    `endif
+
+
+
+
+    // #2 clr = 1;
+    // #2 clr = 0;
     // reg test
     // #2 bus_in_2 = 255;
     // #2 wrZlo = 1;
@@ -163,18 +232,18 @@ module top(input [3:0] SW, output LED_R, output LED_G, output LED_B, output TX,
     // #2 wrInst=1;
 
 
-    #2 bus_in_2 = 5;
-    #2 wrA =1;
-    #2 wrA =0;
+    // #2 bus_in_2 = 5;
+    // #2 wrA =1;
+    // #2 wrA =0;
 
-    #2 bus_in_2 = 2;
-    #2 wrB =1;
-    #2 wrB =0;
+    // #2 bus_in_2 = 2;
+    // #2 wrB =1;
+    // #2 wrB =0;
 
-    #2 bus_in_2 = 0;
-    #2 enAdd = 1;
-    #2 enAdd = 0;
-    #2 enSub = 1;
+    // #2 bus_in_2 = 0;
+    // #2 enAdd = 1;
+    // #2 enAdd = 0;
+    // #2 enSub = 1;
 
 
     // #20 $finish;