add alu

.gitignore

+icarusTest
+top.asc
+top.bin
+wave.vcd

alu.v

+module alu(
+    input clk,
+    input wrA,
+    input wrB,
+    input enAdd,
+    input enSub,
+    input clr,
+    input [15:0] busIn,
+    output [15:0] busOut
+);
+
+  wire [15:0] aVal;
+  wire [7:0] aValLo;
+  wire [7:0] aValHi;
+  assign aVal = {aValHi, aValLo};
+
+  register aReg (
+    .clk(clk),
+    .clr(clr),
+    .in(busIn),
+    .wrHi(wrA),
+    .wrLo(wrA),
+    .enHi(1'b0),
+    .enLo(1'b0),
+    .currentHi(aValHi),
+    .currentLo(aValLo)
+  );
+
+  wire [15:0] bVal;
+  wire [7:0] bValLo;
+  wire [7:0] bValHi;
+  assign bVal = {bValHi, bValLo};
+
+  register bReg (
+    .clk(clk),
+    .clr(clr),
+    .in(busIn),
+    .wrHi(wrB),
+    .wrLo(wrB),
+    .enHi(1'b0),
+    .enLo(1'b0),
+    .currentHi(bValHi),
+    .currentLo(bValLo)
+  );
+
+  assign busOut = enAdd ? aVal + bVal : (enSub ? aVal - bVal : 15'b0);
+endmodule
\ No newline at end of file

top.v

@@ -3,6 +3,7 @@
 `include "register.v"
 `include "ram.v"
 `include "pc.v"
+`include "alu.v"
 
 
 module top(input [3:0] SW, output LED_R, output LED_G, output LED_B, output TX, input P3_10);
@@ -12,10 +13,11 @@ module top(input [3:0] SW, output LED_R, output LED_G, output LED_B, output TX,
   wire [15:0] bus_in_3;
   wire [15:0] bus_in_4;
   wire [15:0] bus_in_5;
+  wire [15:0] bus_in_6;
   reg [15:0] bus_in_2 = 0;
 
   wire [15:0] bus_out;
-  assign bus_out = bus_in_1 | bus_in_2 | bus_in_3 | bus_in_4 | bus_in_5;
+  assign bus_out = bus_in_1 | bus_in_2 | bus_in_3 | bus_in_4 | bus_in_5 | bus_in_6;
 
   reg [22:0] clock_div;
   reg sClk;
@@ -92,6 +94,22 @@ module top(input [3:0] SW, output LED_R, output LED_G, output LED_B, output TX,
                     );
 
 
+  reg wrA = 0;
+  reg wrB = 0;
+  reg enSub = 0;
+  reg enAdd = 0;
+
+  alu alu(
+      .clk(clk),
+      .wrA(wrA),
+      .wrB(wrB),
+      .enAdd(enAdd),
+      .enSub(enSub),
+      .clr(clr),
+      .busIn(bus_out),
+      .busOut(bus_in_6)
+  );
+
   initial begin
     $readmemh("control.mem", controlMemory);
     $dumpfile("wave.vcd");
@@ -140,15 +158,26 @@ module top(input [3:0] SW, output LED_R, output LED_G, output LED_B, output TX,
     // #2 enRam = 1;
     // #2 enRam = 0;
 
-    #2 incPc = 1;
 
-    #2 enPc = 1;
 
     // #2 wrInst=1;
 
 
+    #2 bus_in_2 = 5;
+    #2 wrA =1;
+    #2 wrA =0;
+
+    #2 bus_in_2 = 2;
+    #2 wrB =1;
+    #2 wrB =0;
+
+    #2 bus_in_2 = 0;
+    #2 enAdd = 1;
+    #2 enAdd = 0;
+    #2 enSub = 1;
+
 
-    #20 $finish;
+    // #20 $finish;
   end
 
   // reg [7:0] comp1;