lantiq: drop kernel 5.4 support

The current state of the kernel 5.4 support is in the openwrt-21.02
branch. No need to keep a not default used kernel in this branch.

Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Tested-by: Stefan Lippers-Hollmann <s.l-h@gmx.de> [VRX268/ bthub5]

target/linux/lantiq/ase/config-5.4

-CONFIG_ADM6996_PHY=y
-CONFIG_ARCH_HAS_PTE_SPECIAL=y
-CONFIG_CPU_MIPS32_R1=y
-# CONFIG_CPU_MIPS32_R2 is not set
-CONFIG_CPU_MIPSR1=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_ACOMP2=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_FIRMWARE_MEMMAP=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-# CONFIG_ISDN is not set
-CONFIG_LANTIQ_ETOP=y
-CONFIG_NLS=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SOC_AMAZON_SE=y
-# CONFIG_SOC_XWAY is not set
-CONFIG_SWCONFIG=y
-CONFIG_TARGET_ISA_REV=1
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_SUPPORT=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y

target/linux/lantiq/config-5.4

-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_CLOCKSOURCE_DATA=y
-CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y
-CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
-CONFIG_ARCH_HAS_DMA_WRITE_COMBINE=y
-CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
-CONFIG_ARCH_HAS_UNCACHED_SEGMENT=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MMAP_RND_BITS_MAX=15
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_USE_BUILTIN_BSWAP=y
-CONFIG_ARCH_USE_MEMREMAP_PROT=y
-CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
-CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
-CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_CEVT_R4K=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CPU_BIG_ENDIAN=y
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_LOAD_STORE_LR=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_RIXI=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CPU_SUPPORTS_MSA=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CSRC_R4K=y
-CONFIG_DMA_NONCOHERENT=y
-CONFIG_DMA_NONCOHERENT_CACHE_SYNC=y
-CONFIG_DTC=y
-# CONFIG_DT_EASY50712 is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_EFI_EARLYCON=y
-CONFIG_ETHERNET_PACKET_MANGLE=y
-CONFIG_FIXED_PHY=y
-CONFIG_FONT_8x16=y
-CONFIG_FONT_AUTOSELECT=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_IPI=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_LIB_ASHLDI3=y
-CONFIG_GENERIC_LIB_ASHRDI3=y
-CONFIG_GENERIC_LIB_CMPDI2=y
-CONFIG_GENERIC_LIB_LSHRDI3=y
-CONFIG_GENERIC_LIB_UCMPDI2=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_MM_LANTIQ=y
-CONFIG_GPIO_STP_XWAY=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_ARCH_COMPILER_H=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_ASM_MODVERSIONS=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_COPY_THREAD_TLS=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FAST_GUP=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_VDSO=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IOREMAP_PROT=y
-CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_KVM=y
-CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PCI=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_RSEQ=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_HW_RANDOM=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_MIPS_CPU=y
-CONFIG_IRQ_WORK=y
-CONFIG_LANTIQ=y
-CONFIG_LANTIQ_DT_NONE=y
-# CONFIG_LANTIQ_ETOP is not set
-CONFIG_LANTIQ_WDT=y
-# CONFIG_LANTIQ_XRX200 is not set
-CONFIG_LEDS_GPIO=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_CORE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MIPS=y
-CONFIG_MIPS_ASID_BITS=8
-CONFIG_MIPS_ASID_SHIFT=0
-CONFIG_MIPS_CLOCK_VSYSCALL=y
-# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set
-# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
-CONFIG_MIPS_CMDLINE_FROM_DTB=y
-# CONFIG_MIPS_ELF_APPENDED_DTB is not set
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-# CONFIG_MIPS_MT_SMP is not set
-# CONFIG_MIPS_NO_APPENDED_DTB is not set
-CONFIG_MIPS_RAW_APPENDED_DTB=y
-CONFIG_MIPS_SPRAM=y
-# CONFIG_MIPS_VPE_LOADER is not set
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_LANTIQ=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_BRNIMAGE_FW=y
-CONFIG_MTD_SPLIT_EVA_FW=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_TPLINK_FW=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-CONFIG_NVMEM=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_NET=y
-CONFIG_PCI_DRIVERS_LEGACY=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHY_LANTIQ_RCU_USB2=y
-# CONFIG_PHY_LANTIQ_VRX200_PCIE is not set
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_LANTIQ=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PINCTRL_XWAY=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_SYSCON=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESET_LANTIQ=y
-# CONFIG_SERIAL_8250 is not set
-CONFIG_SERIAL_LANTIQ=y
-# CONFIG_SOC_AMAZON_SE is not set
-# CONFIG_SOC_FALCON is not set
-CONFIG_SOC_TYPE_XWAY=y
-CONFIG_SOC_XWAY=y
-CONFIG_SPI=y
-CONFIG_SPI_LANTIQ_SSC=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SRCU=y
-CONFIG_SWAP_IO_SPACE=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
-CONFIG_SYS_SUPPORTS_MIPS16=y
-CONFIG_SYS_SUPPORTS_MULTITHREADING=y
-CONFIG_SYS_SUPPORTS_VPE_LOADER=y
-CONFIG_TARGET_ISA_REV=2
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TINY_SRCU=y
-CONFIG_USE_OF=y
-CONFIG_WATCHDOG_CORE=y

target/linux/lantiq/falcon/config-5.4

-CONFIG_LANTIQ_ETOP=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_SPLIT_FIRMWARE_NAME="linux"
-CONFIG_PINCTRL_FALCON=y
-CONFIG_SOC_FALCON=y
-# CONFIG_SOC_XWAY is not set
-CONFIG_SPI_FALCON=y

target/linux/lantiq/patches-5.4/0004-MIPS-lantiq-add-atm-hack.patch

-From 9afadf01b1be371ee88491819aa67364684461f9 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Fri, 3 Aug 2012 10:27:25 +0200
-Subject: [PATCH 04/36] MIPS: lantiq: add atm hack
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/include/asm/mach-lantiq/lantiq_atm.h |  196 +++++++++++++++++++++++
- arch/mips/include/asm/mach-lantiq/lantiq_ptm.h |  203 ++++++++++++++++++++++++
- arch/mips/lantiq/irq.c                         |    2 +
- arch/mips/mm/cache.c                           |    4 +
- include/uapi/linux/atm.h                       |    6 +
- net/atm/common.c                               |    6 +
- net/atm/proc.c                                 |    2 +-
- 7 files changed, 416 insertions(+), 1 deletion(-)
- create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_atm.h
- create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_ptm.h
-
---- /dev/null
-+++ b/arch/mips/include/asm/mach-lantiq/lantiq_atm.h
-@@ -0,0 +1,196 @@
-+/******************************************************************************
-+**
-+** FILE NAME    : ifx_atm.h
-+** PROJECT      : UEIP
-+** MODULES      : ATM
-+**
-+** DATE         : 17 Jun 2009
-+** AUTHOR       : Xu Liang
-+** DESCRIPTION  : Global ATM driver header file
-+** COPYRIGHT    :       Copyright (c) 2006
-+**                      Infineon Technologies AG
-+**                      Am Campeon 1-12, 85579 Neubiberg, Germany
-+**
-+**    This program is free software; you can redistribute it and/or modify
-+**    it under the terms of the GNU General Public License as published by
-+**    the Free Software Foundation; either version 2 of the License, or
-+**    (at your option) any later version.
-+**
-+** HISTORY
-+** $Date        $Author         $Comment
-+** 07 JUL 2009  Xu Liang        Init Version
-+*******************************************************************************/
-+
-+#ifndef IFX_ATM_H
-+#define IFX_ATM_H
-+
-+
-+
-+/*!
-+  \defgroup IFX_ATM UEIP Project - ATM driver module
-+  \brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9.
-+ */
-+
-+/*!
-+  \defgroup IFX_ATM_IOCTL IOCTL Commands
-+  \ingroup IFX_ATM
-+  \brief IOCTL Commands used by user application.
-+ */
-+
-+/*!
-+  \defgroup IFX_ATM_STRUCT Structures
-+  \ingroup IFX_ATM
-+  \brief Structures used by user application.
-+ */
-+
-+/*!
-+  \file ifx_atm.h
-+  \ingroup IFX_ATM
-+  \brief ATM driver header file
-+ */
-+
-+
-+
-+/*
-+ * ####################################
-+ *              Definition
-+ * ####################################
-+ */
-+
-+/*!
-+  \addtogroup IFX_ATM_STRUCT
-+ */
-+/*@{*/
-+
-+/*
-+ *  ATM MIB
-+ */
-+
-+/*!
-+  \struct atm_cell_ifEntry_t
-+  \brief Structure used for Cell Level MIB Counters.
-+
-+  User application use this structure to call IOCTL command "PPE_ATM_MIB_CELL".
-+ */
-+typedef struct {
-+	__u32	ifHCInOctets_h;     /*!< byte counter of ingress cells (upper 32 bits, total 64 bits)   */
-+	__u32	ifHCInOctets_l;     /*!< byte counter of ingress cells (lower 32 bits, total 64 bits)   */
-+	__u32	ifHCOutOctets_h;    /*!< byte counter of egress cells (upper 32 bits, total 64 bits)    */
-+	__u32	ifHCOutOctets_l;    /*!< byte counter of egress cells (lower 32 bits, total 64 bits)    */
-+	__u32	ifInErrors;         /*!< counter of error ingress cells     */
-+	__u32	ifInUnknownProtos;  /*!< counter of unknown ingress cells   */
-+	__u32	ifOutErrors;        /*!< counter of error egress cells      */
-+} atm_cell_ifEntry_t;
-+
-+/*!
-+  \struct atm_aal5_ifEntry_t
-+  \brief Structure used for AAL5 Frame Level MIB Counters.
-+
-+  User application use this structure to call IOCTL command "PPE_ATM_MIB_AAL5".
-+ */
-+typedef struct {
-+	__u32	ifHCInOctets_h;     /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */
-+	__u32	ifHCInOctets_l;     /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */
-+	__u32	ifHCOutOctets_h;    /*!< byte counter of egress packets (upper 32 bits, total 64 bits)  */
-+	__u32	ifHCOutOctets_l;    /*!< byte counter of egress packets (lower 32 bits, total 64 bits)  */
-+	__u32	ifInUcastPkts;      /*!< counter of ingress packets         */
-+	__u32	ifOutUcastPkts;     /*!< counter of egress packets          */
-+	__u32	ifInErrors;         /*!< counter of error ingress packets   */
-+	__u32	ifInDiscards;       /*!< counter of dropped ingress packets */
-+	__u32	ifOutErros;         /*!< counter of error egress packets    */
-+	__u32	ifOutDiscards;      /*!< counter of dropped egress packets  */
-+} atm_aal5_ifEntry_t;
-+
-+/*!
-+  \struct atm_aal5_vcc_t
-+  \brief Structure used for per PVC AAL5 Frame Level MIB Counters.
-+
-+  This structure is a part of structure "atm_aal5_vcc_x_t".
-+ */
-+typedef struct {
-+	__u32	aal5VccCrcErrors;       /*!< counter of ingress packets with CRC error  */
-+	__u32	aal5VccSarTimeOuts;     /*!< counter of ingress packets with Re-assemble timeout    */  //no timer support yet
-+	__u32	aal5VccOverSizedSDUs;   /*!< counter of oversized ingress packets       */
-+} atm_aal5_vcc_t;
-+
-+/*!
-+  \struct atm_aal5_vcc_x_t
-+  \brief Structure used for per PVC AAL5 Frame Level MIB Counters.
-+
-+  User application use this structure to call IOCTL command "PPE_ATM_MIB_VCC".
-+ */
-+typedef struct {
-+	int             vpi;        /*!< VPI of the VCC to get MIB counters */
-+	int             vci;        /*!< VCI of the VCC to get MIB counters */
-+	atm_aal5_vcc_t  mib_vcc;    /*!< structure to get MIB counters      */
-+} atm_aal5_vcc_x_t;
-+
-+/*@}*/
-+
-+
-+
-+/*
-+ * ####################################
-+ *                IOCTL
-+ * ####################################
-+ */
-+
-+/*!
-+  \addtogroup IFX_ATM_IOCTL
-+ */
-+/*@{*/
-+
-+/*
-+ *  ioctl Command
-+ */
-+/*!
-+  \brief ATM IOCTL Magic Number
-+ */
-+#define PPE_ATM_IOC_MAGIC       'o'
-+/*!
-+  \brief ATM IOCTL Command - Get Cell Level MIB Counters
-+
-+   This command is obsolete. User can get cell level MIB from DSL API.
-+   This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters.
-+ */
-+#define PPE_ATM_MIB_CELL        _IOW(PPE_ATM_IOC_MAGIC,  0, atm_cell_ifEntry_t)
-+/*!
-+  \brief ATM IOCTL Command - Get AAL5 Level MIB Counters
-+
-+   Get AAL5 packet counters.
-+   This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters.
-+ */
-+#define PPE_ATM_MIB_AAL5        _IOW(PPE_ATM_IOC_MAGIC,  1, atm_aal5_ifEntry_t)
-+/*!
-+  \brief ATM IOCTL Command - Get Per PVC MIB Counters
-+
-+   Get AAL5 packet counters for each PVC.
-+   This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters.
-+ */
-+#define PPE_ATM_MIB_VCC         _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t)
-+/*!
-+  \brief Total Number of ATM IOCTL Commands
-+ */
-+#define PPE_ATM_IOC_MAXNR       3
-+
-+/*@}*/
-+
-+
-+
-+/*
-+ * ####################################
-+ *                 API
-+ * ####################################
-+ */
-+
-+#ifdef __KERNEL__
-+struct port_cell_info {
-+    unsigned int    port_num;
-+    unsigned int    tx_link_rate[2];
-+};
-+#endif
-+
-+
-+
-+#endif  //  IFX_ATM_H
-+
---- /dev/null
-+++ b/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h
-@@ -0,0 +1,203 @@
-+/******************************************************************************
-+**
-+** FILE NAME    : ifx_ptm.h
-+** PROJECT      : UEIP
-+** MODULES      : PTM
-+**
-+** DATE         : 17 Jun 2009
-+** AUTHOR       : Xu Liang
-+** DESCRIPTION  : Global PTM driver header file
-+** COPYRIGHT    :       Copyright (c) 2006
-+**                      Infineon Technologies AG
-+**                      Am Campeon 1-12, 85579 Neubiberg, Germany
-+**
-+**    This program is free software; you can redistribute it and/or modify
-+**    it under the terms of the GNU General Public License as published by
-+**    the Free Software Foundation; either version 2 of the License, or
-+**    (at your option) any later version.
-+**
-+** HISTORY
-+** $Date        $Author         $Comment
-+** 07 JUL 2009  Xu Liang        Init Version
-+*******************************************************************************/
-+
-+#ifndef IFX_PTM_H
-+#define IFX_PTM_H
-+
-+
-+
-+/*!
-+  \defgroup IFX_PTM UEIP Project - PTM driver module
-+  \brief UEIP Project - PTM driver module, support Danube, Amazon-SE, AR9, VR9.
-+ */
-+
-+/*!
-+  \defgroup IFX_PTM_IOCTL IOCTL Commands
-+  \ingroup IFX_PTM
-+  \brief IOCTL Commands used by user application.
-+ */
-+
-+/*!
-+  \defgroup IFX_PTM_STRUCT Structures
-+  \ingroup IFX_PTM
-+  \brief Structures used by user application.
-+ */
-+
-+/*!
-+  \file ifx_ptm.h
-+  \ingroup IFX_PTM
-+  \brief PTM driver header file
-+ */
-+
-+
-+
-+/*
-+ * ####################################
-+ *              Definition
-+ * ####################################
-+ */
-+
-+
-+
-+/*
-+ * ####################################
-+ *                IOCTL
-+ * ####################################
-+ */
-+
-+/*!
-+  \addtogroup IFX_PTM_IOCTL
-+ */
-+/*@{*/
-+
-+/*
-+ *  ioctl Command
-+ */
-+/*!
-+  \brief PTM IOCTL Command - Get codeword MIB counters.
-+
-+  This command uses structure "PTM_CW_IF_ENTRY_T" to get codeword level MIB counters.
-+ */
-+#define IFX_PTM_MIB_CW_GET              SIOCDEVPRIVATE + 1
-+/*!
-+  \brief PTM IOCTL Command - Get packet MIB counters.
-+
-+  This command uses structure "PTM_FRAME_MIB_T" to get packet level MIB counters.
-+ */
-+#define IFX_PTM_MIB_FRAME_GET           SIOCDEVPRIVATE + 2
-+/*!
-+  \brief PTM IOCTL Command - Get firmware configuration (CRC).
-+
-+  This command uses structure "IFX_PTM_CFG_T" to get firmware configuration (CRC).
-+ */
-+#define IFX_PTM_CFG_GET                 SIOCDEVPRIVATE + 3
-+/*!
-+  \brief PTM IOCTL Command - Set firmware configuration (CRC).
-+
-+  This command uses structure "IFX_PTM_CFG_T" to set firmware configuration (CRC).
-+ */
-+#define IFX_PTM_CFG_SET                 SIOCDEVPRIVATE + 4
-+/*!
-+  \brief PTM IOCTL Command - Program priority value to TX queue mapping.
-+
-+  This command uses structure "IFX_PTM_PRIO_Q_MAP_T" to program priority value to TX queue mapping.
-+ */
-+#define IFX_PTM_MAP_PKT_PRIO_TO_Q       SIOCDEVPRIVATE + 14
-+
-+/*@}*/
-+
-+
-+/*!
-+  \addtogroup IFX_PTM_STRUCT
-+ */
-+/*@{*/
-+
-+/*
-+ *  ioctl Data Type
-+ */
-+
-+/*!
-+  \typedef PTM_CW_IF_ENTRY_T
-+  \brief Wrapping of structure "ptm_cw_ifEntry_t".
-+ */
-+/*!
-+  \struct ptm_cw_ifEntry_t
-+  \brief Structure used for CodeWord level MIB counters.
-+ */
-+typedef struct ptm_cw_ifEntry_t {
-+    uint32_t    ifRxNoIdleCodewords;    /*!< output, number of ingress user codeword */
-+    uint32_t    ifRxIdleCodewords;      /*!< output, number of ingress idle codeword */
-+    uint32_t    ifRxCodingViolation;    /*!< output, number of error ingress codeword */
-+    uint32_t    ifTxNoIdleCodewords;    /*!< output, number of egress user codeword */
-+    uint32_t    ifTxIdleCodewords;      /*!< output, number of egress idle codeword */
-+} PTM_CW_IF_ENTRY_T;
-+
-+/*!
-+  \typedef PTM_FRAME_MIB_T
-+  \brief Wrapping of structure "ptm_frame_mib_t".
-+ */
-+/*!
-+  \struct ptm_frame_mib_t
-+  \brief Structure used for packet level MIB counters.
-+ */
-+typedef struct ptm_frame_mib_t {
-+    uint32_t    RxCorrect;      /*!< output, number of ingress packet */
-+    uint32_t    TC_CrcError;    /*!< output, number of egress packet with CRC error */
-+    uint32_t    RxDropped;      /*!< output, number of dropped ingress packet */
-+    uint32_t    TxSend;         /*!< output, number of egress packet */
-+} PTM_FRAME_MIB_T;
-+
-+/*!
-+  \typedef IFX_PTM_CFG_T
-+  \brief Wrapping of structure "ptm_cfg_t".
-+ */
-+/*!
-+  \struct ptm_cfg_t
-+  \brief Structure used for ETH/TC CRC configuration.
-+ */
-+typedef struct ptm_cfg_t {
-+    uint32_t    RxEthCrcPresent;    /*!< input/output, ingress packet has ETH CRC */
-+    uint32_t    RxEthCrcCheck;      /*!< input/output, check ETH CRC of ingress packet */
-+    uint32_t    RxTcCrcCheck;       /*!< input/output, check TC CRC of ingress codeword */
-+    uint32_t    RxTcCrcLen;         /*!< input/output, length of TC CRC of ingress codeword */
-+    uint32_t    TxEthCrcGen;        /*!< input/output, generate ETH CRC for egress packet */
-+    uint32_t    TxTcCrcGen;         /*!< input/output, generate TC CRC for egress codeword */
-+    uint32_t    TxTcCrcLen;         /*!< input/output, length of TC CRC of egress codeword */
-+} IFX_PTM_CFG_T;
-+
-+/*!
-+  \typedef IFX_PTM_PRIO_Q_MAP_T
-+  \brief Wrapping of structure "ppe_prio_q_map".
-+ */
-+/*!
-+  \struct ppe_prio_q_map
-+  \brief Structure used for Priority Value to TX Queue mapping.
-+ */
-+typedef struct ppe_prio_q_map {
-+    int             pkt_prio;
-+    int             qid;
-+    int             vpi;    //  ignored in eth interface
-+    int             vci;    //  ignored in eth interface
-+} IFX_PTM_PRIO_Q_MAP_T;
-+
-+/*@}*/
-+
-+
-+
-+/*
-+ * ####################################
-+ *                 API
-+ * ####################################
-+ */
-+
-+#ifdef __KERNEL__
-+struct port_cell_info {
-+    unsigned int    port_num;
-+    unsigned int    tx_link_rate[2];
-+};
-+#endif
-+
-+
-+
-+#endif  //  IFX_PTM_H
-+
---- a/arch/mips/lantiq/irq.c
-+++ b/arch/mips/lantiq/irq.c
-@@ -12,6 +12,7 @@
- #include <linux/of_platform.h>
- #include <linux/of_address.h>
- #include <linux/of_irq.h>
-+#include <linux/module.h>
- 
- #include <asm/bootinfo.h>
- #include <asm/irq_cpu.h>
-@@ -91,6 +92,7 @@ void ltq_disable_irq(struct irq_data *d)
- 	}
- 	raw_spin_unlock_irqrestore(&ltq_icu_lock, flags);
- }
-+EXPORT_SYMBOL(ltq_mask_and_ack_irq);
- 
- void ltq_mask_and_ack_irq(struct irq_data *d)
- {
---- a/arch/mips/mm/cache.c
-+++ b/arch/mips/mm/cache.c
-@@ -62,6 +62,10 @@ void (*_dma_cache_wback_inv)(unsigned lo
- void (*_dma_cache_wback)(unsigned long start, unsigned long size);
- void (*_dma_cache_inv)(unsigned long start, unsigned long size);
- 
-+EXPORT_SYMBOL(_dma_cache_wback_inv);
-+EXPORT_SYMBOL(_dma_cache_wback);
-+EXPORT_SYMBOL(_dma_cache_inv);
-+
- #endif /* CONFIG_DMA_NONCOHERENT */
- 
- /*
---- a/include/uapi/linux/atm.h
-+++ b/include/uapi/linux/atm.h
-@@ -131,8 +131,14 @@
- #define ATM_ABR		4
- #define ATM_ANYCLASS	5		/* compatible with everything */
- 
-+#define ATM_VBR_NRT     ATM_VBR
-+#define ATM_VBR_RT      6
-+#define ATM_UBR_PLUS    7
-+#define ATM_GFR         8
-+
- #define ATM_MAX_PCR	-1		/* maximum available PCR */
- 
-+
- struct atm_trafprm {
- 	unsigned char	traffic_class;	/* traffic class (ATM_UBR, ...) */
- 	int		max_pcr;	/* maximum PCR in cells per second */
---- a/net/atm/proc.c
-+++ b/net/atm/proc.c
-@@ -141,7 +141,7 @@ static void *vcc_seq_next(struct seq_fil
- static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc)
- {
- 	static const char *const class_name[] = {
--		"off", "UBR", "CBR", "VBR", "ABR"};
-+		"off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"};
- 	static const char *const aal_name[] = {
- 		"---",	"1",	"2",	"3/4",	/*  0- 3 */
- 		"???",	"5",	"???",	"???",	/*  4- 7 */

target/linux/lantiq/patches-5.4/0018-MTD-nand-lots-of-xrx200-fixes.patch

-From 997a8965db8417266bea3fbdcfa3e5655a1b52fa Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Tue, 9 Sep 2014 23:12:15 +0200
-Subject: [PATCH 18/36] MTD: nand: lots of xrx200 fixes
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/mtd/nand/raw/xway_nand.c |   63 ++++++++++++++++++++++++++++++++++++++++++
- 1 file changed, 63 insertions(+)
-
---- a/drivers/mtd/nand/raw/xway_nand.c
-+++ b/drivers/mtd/nand/raw/xway_nand.c
-@@ -61,6 +61,24 @@
- #define NAND_CON_CSMUX		(1 << 1)
- #define NAND_CON_NANDM		1
- 
-+#define DANUBE_PCI_REG32( addr )    (*(volatile u32 *)(addr))
-+#define PCI_CR_PR_OFFSET	    (KSEG1+0x1E105400)
-+#define PCI_CR_PC_ARB		    (PCI_CR_PR_OFFSET + 0x0080)
-+
-+/*
-+ * req_mask provides a mechanism to prevent interference between
-+ * nand and pci (probably only relevant for the BT Home Hub 2B).
-+ * Setting it causes the corresponding pci req pins to be masked
-+ * during nand access, and also moves ebu locking from the read/write
-+ * functions to the chip select function to ensure that the whole
-+ * operation runs with interrupts disabled.
-+ * In addition it switches on some extra waiting in xway_cmd_ctrl().
-+ * This seems to be necessary if the ebu_cs1 pin has open-drain disabled,
-+ * which in turn seems to be necessary for the nor chip to be recognised
-+ * reliably, on a board (Home Hub 2B again) which has both nor and nand.
-+ */
-+static __be32 req_mask = 0;
-+
- struct xway_nand_data {
- 	struct nand_chip	chip;
- 	unsigned long		csflags;
-@@ -91,10 +109,22 @@ static void xway_select_chip(struct nand
- 	case -1:
- 		ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON);
- 		ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON);
-+
-+		if (req_mask) {
-+			/* Unmask all external PCI request */
-+			DANUBE_PCI_REG32(PCI_CR_PC_ARB) &= ~(req_mask << 16);
-+		}
-+
- 		spin_unlock_irqrestore(&ebu_lock, data->csflags);
- 		break;
- 	case 0:
- 		spin_lock_irqsave(&ebu_lock, data->csflags);
-+
-+		if (req_mask) {
-+			/* Mask all external PCI request */
-+			DANUBE_PCI_REG32(PCI_CR_PC_ARB) |= (req_mask << 16);
-+		}
-+
- 		ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON);
- 		ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON);
- 		break;
-@@ -107,6 +137,11 @@ static void xway_cmd_ctrl(struct nand_ch
- {
- 	struct mtd_info *mtd = nand_to_mtd(chip);
- 
-+	if (req_mask) {
-+		if (cmd != NAND_CMD_STATUS)
-+			ltq_ebu_w32(0, EBU_NAND_WAIT); /* Clear nand ready */
-+	}
-+
- 	if (cmd == NAND_CMD_NONE)
- 		return;
- 
-@@ -117,6 +152,24 @@ static void xway_cmd_ctrl(struct nand_ch
- 
- 	while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
- 		;
-+
-+	if (req_mask) {
-+	       /*
-+		* program and erase have their own busy handlers
-+		* status and sequential in needs no delay
-+		*/
-+		switch (cmd) {
-+			case NAND_CMD_ERASE1:
-+			case NAND_CMD_SEQIN:
-+			case NAND_CMD_STATUS:
-+			case NAND_CMD_READID:
-+			return;
-+		}
-+
-+		/* wait until command is processed */
-+		while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD) == 0)
-+			;
-+	}
- }
- 
- static int xway_dev_ready(struct nand_chip *chip)
-@@ -156,6 +209,7 @@ static int xway_nand_probe(struct platfo
- 	int err;
- 	u32 cs;
- 	u32 cs_flag = 0;
-+	const __be32 *req_mask_ptr;
- 
- 	/* Allocate memory for the device structure (and zero it) */
- 	data = devm_kzalloc(&pdev->dev, sizeof(struct xway_nand_data),
-@@ -191,6 +245,15 @@ static int xway_nand_probe(struct platfo
- 	if (!err && cs == 1)
- 		cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1;
- 
-+	req_mask_ptr = of_get_property(pdev->dev.of_node,
-+					"req-mask", NULL);
-+
-+	/*
-+	 * Load the PCI req lines to mask from the device tree. If the
-+	 * property is not present, setting req_mask to 0 disables masking.
-+	 */
-+	req_mask = (req_mask_ptr ? *req_mask_ptr : 0);
-+
- 	/* setup the EBU to run in NAND mode on our base addr */
- 	ltq_ebu_w32(CPHYSADDR(data->nandaddr)
- 		    | ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1);

target/linux/lantiq/patches-5.4/0019-MTD-nand-support-new-dt-bindings.patch

-The nand-ecc-mode DT binding is depracated but the new bindings are
-not supported by kernel 5.4. Based on a fix in the kernel to not
-overwrite the DT ECC settings, the DT needs to be updated and moves
-to the new DT binding.
-Since the DT is shared between kernel 5.4 and 5.10, this patch is
-an interim solution to allow to use the new DT bindings in kernel 5.4.
-It should be removed when moving away from kernel 5.4.
---- a/drivers/mtd/nand/raw/nand_base.c
-+++ b/drivers/mtd/nand/raw/nand_base.c
-@@ -4851,10 +4851,17 @@ static int of_get_nand_ecc_mode(struct d
- {
- 	const char *pm;
- 	int err, i;
-+	struct device_node *eng_np;
- 
- 	err = of_property_read_string(np, "nand-ecc-mode", &pm);
--	if (err < 0)
-+	if (err < 0) {
-+		if (of_property_read_bool(np, "nand-use-soft-ecc-engine"))
-+			return NAND_ECC_SOFT;
-+		eng_np = of_parse_phandle(np, "nand-ecc-engine", 0);
-+		if (eng_np && (eng_np == np))
-+			return NAND_ECC_ON_DIE;
- 		return err;
-+	}
- 
- 	for (i = 0; i < ARRAY_SIZE(nand_ecc_modes); i++)
- 		if (!strcasecmp(pm, nand_ecc_modes[i]))

target/linux/lantiq/patches-5.4/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch

-From e3b20f04e9f9cae1babe091fdc1d08d7703ae344 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Thu, 7 Aug 2014 18:18:00 +0200
-Subject: [PATCH 20/36] MTD: lantiq: handle NO_XIP on cfi0001 flash
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/mtd/maps/lantiq-flash.c |    6 +++++-
- 1 file changed, 5 insertions(+), 1 deletion(-)
-
---- a/drivers/mtd/maps/lantiq-flash.c
-+++ b/drivers/mtd/maps/lantiq-flash.c
-@@ -129,7 +129,11 @@ ltq_mtd_probe(struct platform_device *pd
- 	if (!ltq_mtd->map)
- 		return -ENOMEM;
- 
--	ltq_mtd->map->phys = ltq_mtd->res->start;
-+	if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL))
-+		ltq_mtd->map->phys = NO_XIP;
-+	else
-+		ltq_mtd->map->phys = ltq_mtd->res->start;
-+	ltq_mtd->res->start;
- 	ltq_mtd->map->size = resource_size(ltq_mtd->res);
- 	ltq_mtd->map->virt = devm_ioremap_resource(&pdev->dev, ltq_mtd->res);
- 	if (IS_ERR(ltq_mtd->map->virt))

target/linux/lantiq/patches-5.4/0023-NET-PHY-add-led-support-for-intel-xway.patch

-From 0a63ab263725c427051a8bbaa0732b749627da27 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Thu, 7 Aug 2014 18:15:36 +0200
-Subject: [PATCH 23/36] NET: PHY: adds driver for lantiq PHY11G
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/net/phy/Kconfig  |    5 +
- drivers/net/phy/Makefile |    1 +
- drivers/net/phy/lantiq.c |  231 ++++++++++++++++++++++++++++++++++++++++++++++
- 3 files changed, 237 insertions(+)
- create mode 100644 drivers/net/phy/lantiq.c
-
---- a/drivers/net/phy/intel-xway.c
-+++ b/drivers/net/phy/intel-xway.c
-@@ -157,6 +157,51 @@
- #define PHY_ID_PHY11G_VR9_1_2		0xD565A409
- #define PHY_ID_PHY22F_VR9_1_2		0xD565A419
- 
-+#if IS_ENABLED(CONFIG_OF_MDIO)
-+static int vr9_gphy_of_reg_init(struct phy_device *phydev)
-+{
-+	u32 tmp;
-+
-+	/* store the led values if one was passed by the devicetree */
-+	if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,ledch", &tmp))
-+		phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCH, tmp);
-+
-+	if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,ledcl", &tmp))
-+		phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCL, tmp);
-+
-+	if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led0h", &tmp))
-+		phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0H, tmp);
-+
-+	if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led0l", &tmp))
-+		phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0L, tmp);
-+
-+	if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led1h", &tmp))
-+		phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1H, tmp);
-+
-+	if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led1l", &tmp))
-+		phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1L, tmp);
-+
-+	if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led2h", &tmp))
-+		phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H,  tmp);
-+
-+	if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led2l", &tmp))
-+		phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, tmp);
-+
-+	if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led3h", &tmp))
-+		phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3H, tmp);
-+
-+	if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led3l", &tmp))
-+		phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3L, tmp);
-+
-+	return 0;
-+}
-+#else
-+static int vr9_gphy_of_reg_init(struct phy_device *phydev)
-+{
-+	return 0;
-+}
-+#endif /* CONFIG_OF_MDIO */
-+
- static int xway_gphy_config_init(struct phy_device *phydev)
- {
- 	int err;
-@@ -204,6 +249,7 @@ static int xway_gphy_config_init(struct
- 	phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, ledxh);
- 	phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, ledxl);
- 
-+	vr9_gphy_of_reg_init(phydev);
- 	return 0;
- }
- 
---- /dev/null
-+++ b/Documentation/devicetree/bindings/phy/phy-lanitq.txt
-@@ -0,0 +1,216 @@
-+Lanitq PHY binding
-+============================================
-+
-+This devicetree binding controls the lantiq ethernet phys led functionality.
-+
-+Example:
-+	mdio@0 {
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		compatible = "lantiq,xrx200-mdio";
-+			phy5: ethernet-phy@5 {
-+			reg = <0x1>;
-+			compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
-+		};
-+		phy11: ethernet-phy@11 {
-+			reg = <0x11>;
-+			compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
-+			lantiq,led2h = <0x00>;
-+			lantiq,led2l = <0x03>;
-+		};
-+		phy12: ethernet-phy@12 {
-+			reg = <0x12>;
-+			compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
-+			lantiq,led1h = <0x00>;
-+			lantiq,led1l = <0x03>;
-+		};
-+		phy13: ethernet-phy@13 {
-+			reg = <0x13>;
-+			compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
-+			lantiq,led2h = <0x00>;
-+			lantiq,led2l = <0x03>;
-+		};
-+		phy14: ethernet-phy@14 {
-+			reg = <0x14>;
-+			compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
-+			lantiq,led1h = <0x00>;
-+			lantiq,led1l = <0x03>;
-+		};
-+	};
-+
-+Register Description
-+============================================
-+
-+LEDCH:
-+
-+Name	Hardware Reset Value
-+LEDCH	0x00C5
-+
-+| 15 |    |    |    |    |    |    |  8 |
-+=========================================
-+|		RES			|
-+=========================================
-+
-+|  7 |    |    |    |    |    |    |  0 |
-+=========================================
-+|   FBF   |   SBF   |RES |     NACS     |
-+=========================================
-+
-+Field	Bits	Type	Description
-+FBF	7:6	RW	Fast Blink Frequency
-+			---
-+			0x0 (00b) F02HZ 2 Hz blinking frequency
-+			0x1 (01b) F04HZ 4 Hz blinking frequency
-+			0x2 (10b) F08HZ 8 Hz blinking frequency
-+			0x3 (11b) F16HZ 16 Hz blinking frequency
-+
-+SBF	5:4	RW	Slow Blink Frequency
-+			---
-+			0x0 (00b) F02HZ 2 Hz blinking frequency
-+			0x1 (01b) F04HZ 4 Hz blinking frequency
-+			0x2 (10b) F08HZ 8 Hz blinking frequency
-+			0x3 (11b) F16HZ 16 Hz blinking frequency
-+
-+NACS	2:0	RW	Inverse of Scan Function
-+			---
-+			0x0 (000b) NONE No Function
-+			0x1 (001b) LINK Complex function enabled when link is up
-+			0x2 (010b) PDOWN Complex function enabled when device is powered-down
-+			0x3 (011b) EEE Complex function enabled when device is in EEE mode
-+			0x4 (100b) ANEG Complex function enabled when auto-negotiation is running
-+			0x5 (101b) ABIST Complex function enabled when analog self-test is running
-+			0x6 (110b) CDIAG Complex function enabled when cable diagnostics are running
-+			0x7 (111b) TEST Complex function enabled when test mode is running
-+
-+LEDCL:
-+
-+Name	Hardware Reset Value
-+LEDCL	0x0067
-+
-+| 15 |    |    |    |    |    |    |  8 |
-+=========================================
-+|		RES			|
-+=========================================
-+
-+|  7 |    |    |    |    |    |    |  0 |
-+=========================================
-+|RES |     SCAN     |RES |    CBLINK    |
-+=========================================
-+
-+Field	Bits	Type	Description
-+SCAN	6:4	RW	Complex Scan Configuration
-+			---
-+			000 B NONE No Function
-+			001 B LINK Complex function enabled when link is up
-+			010 B PDOWN Complex function enabled when device is powered-down
-+			011 B EEE Complex function enabled when device is in EEE mode
-+			100 B ANEG Complex function enabled when auto-negotiation is running
-+			101 B ABIST Complex function enabled when analog self-test is running
-+			110 B CDIAG Complex function enabled when cable diagnostics are running
-+			111 B TEST Complex function enabled when test mode is running
-+
-+CBLINK	2:0	RW	Complex Blinking Configuration
-+			---
-+			000 B NONE No Function
-+			001 B LINK Complex function enabled when link is up
-+			010 B PDOWN Complex function enabled when device is powered-down
-+			011 B EEE Complex function enabled when device is in EEE mode
-+			100 B ANEG Complex function enabled when auto-negotiation is running
-+			101 B ABIST Complex function enabled when analog self-test is running
-+			110 B CDIAG Complex function enabled when cable diagnostics are running
-+			111 B TEST Complex function enabled when test mode is running
-+
-+LEDxH:
-+
-+Name	Hardware Reset Value
-+LED0H	0x0070
-+LED1H	0x0020
-+LED2H	0x0040
-+LED3H	0x0040
-+
-+| 15 |    |    |    |    |    |    |  8 |
-+=========================================
-+|		RES			|
-+=========================================
-+
-+|  7 |    |    |    |    |    |    |  0 |
-+=========================================
-+|        CON        |       BLINKF      |
-+=========================================
-+
-+Field	Bits	Type	Description
-+CON	7:4	RW	Constant On Configuration
-+			---
-+			0x0 (0000b) NONE LED does not light up constantly
-+			0x1 (0001b) LINK10 LED is on when link is 10 Mbit/s
-+			0x2 (0010b) LINK100 LED is on when link is 100 Mbit/s
-+			0x3 (0011b) LINK10X LED is on when link is 10/100 Mbit/s
-+			0x4 (0100b) LINK1000 LED is on when link is 1000 Mbit/s
-+			0x5 (0101b) LINK10_0 LED is on when link is 10/1000 Mbit/s
-+			0x6 (0110b) LINK100X LED is on when link is 100/1000 Mbit/s
-+			0x7 (0111b) LINK10XX LED is on when link is 10/100/1000 Mbit/s
-+			0x8 (1000b) PDOWN LED is on when device is powered-down
-+			0x9 (1001b) EEE LED is on when device is in EEE mode
-+			0xA (1010b) ANEG LED is on when auto-negotiation is running
-+			0xB (1011b) ABIST LED is on when analog self-test is running
-+			0xC (1100b) CDIAG LED is on when cable diagnostics are running
-+
-+BLINKF	3:0	RW	Fast Blinking Configuration
-+			---
-+			0x0 (0000b) NONE No Blinking
-+			0x1 (0001b) LINK10 Blink when link is 10 Mbit/s
-+			0x2 (0010b) LINK100 Blink when link is 100 Mbit/s
-+			0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s
-+			0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s
-+			0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s
-+			0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s
-+			0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s
-+			0x8 (1000b) PDOWN Blink when device is powered-down
-+			0x9 (1001b) EEE Blink when device is in EEE mode
-+			0xA (1010b) ANEG Blink when auto-negotiation is running
-+			0xB (1011b) ABIST Blink when analog self-test is running
-+			0xC (1100b) CDIAG Blink when cable diagnostics are running
-+
-+LEDxL:
-+
-+Name	Hardware Reset Value
-+LED0L	0x0003
-+LED1L	0x0000
-+LED2L	0x0000
-+LED3L	0x0020
-+
-+| 15 |    |    |    |    |    |    |  8 |
-+=========================================
-+|		RES			|
-+=========================================
-+
-+|  7 |    |    |    |    |    |    |  0 |
-+=========================================
-+|      BLINKS       |       PULSE       |
-+=========================================
-+
-+Field	Bits	Type	Description
-+BLINKS	7:4	RW	Slow Blinkin Configuration
-+			---
-+			0x0 (0000b) NONE No Blinking
-+			0x1 (0001b) LINK10 Blink when link is 10 Mbit/s
-+			0x2 (0010b) LINK100 Blink when link is 100 Mbit/s
-+			0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s
-+			0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s
-+			0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s
-+			0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s
-+			0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s
-+			0x8 (1000b) PDOWN Blink when device is powered-down
-+			0x9 (1001b) EEE Blink when device is in EEE mode
-+			0xA (1010b) ANEG Blink when auto-negotiation is running
-+			0xB (1011b) ABIST Blink when analog self-test is running
-+			0xC (1100b) CDIAG Blink when cable diagnostics are runningning
-+
-+PULSE	3:0	RW	Pulsing Configuration
-+			The pulse field is a mask field by which certain events can be combined
-+			---
-+			0x0 (0000b) NONE No pulsing
-+			0x1 (0001b) TXACT Transmit activity
-+			0x2 (0010b) RXACT Receive activity
-+			0x4 (0100b) COL Collision
-+			0x8 (1000b) RES Reserved

target/linux/lantiq/patches-5.4/0030-GPIO-add-named-gpio-exports.patch

-From cc809a441d8f2924f785eb863dfa6aef47a25b0b Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Tue, 12 Aug 2014 20:49:27 +0200
-Subject: [PATCH 30/36] GPIO: add named gpio exports
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/gpio/gpiolib-of.c     |   68 +++++++++++++++++++++++++++++++++++++++++
- drivers/gpio/gpiolib.c        |   11 +++++--
- include/asm-generic/gpio.h    |    5 +++
- include/linux/gpio/consumer.h |    8 +++++
- 4 files changed, 90 insertions(+), 2 deletions(-)
-
---- a/drivers/gpio/gpiolib-of.c
-+++ b/drivers/gpio/gpiolib-of.c
-@@ -19,6 +19,8 @@
- #include <linux/pinctrl/pinctrl.h>
- #include <linux/slab.h>
- #include <linux/gpio/machine.h>
-+#include <linux/init.h>
-+#include <linux/platform_device.h>
- 
- #include "gpiolib.h"
- #include "gpiolib-of.h"
-@@ -915,3 +917,72 @@ void of_gpiochip_remove(struct gpio_chip
- {
- 	of_node_put(chip->of_node);
- }
-+
-+#ifdef CONFIG_GPIO_SYSFS
-+
-+static struct of_device_id gpio_export_ids[] = {
-+	{ .compatible = "gpio-export" },
-+	{ /* sentinel */ }
-+};
-+
-+static int of_gpio_export_probe(struct platform_device *pdev)
-+{
-+	struct device_node *np = pdev->dev.of_node;
-+	struct device_node *cnp;
-+	u32 val;
-+	int nb = 0;
-+
-+	for_each_child_of_node(np, cnp) {
-+		const char *name = NULL;
-+		int gpio;
-+		bool dmc;
-+		int max_gpio = 1;
-+		int i;
-+
-+		of_property_read_string(cnp, "gpio-export,name", &name);
-+
-+		if (!name)
-+			max_gpio = of_gpio_count(cnp);
-+
-+		for (i = 0; i < max_gpio; i++) {
-+			unsigned flags = 0;
-+			enum of_gpio_flags of_flags;
-+
-+			gpio = of_get_gpio_flags(cnp, i, &of_flags);
-+			if (!gpio_is_valid(gpio))
-+				return gpio;
-+
-+			if (of_flags == OF_GPIO_ACTIVE_LOW)
-+				flags |= GPIOF_ACTIVE_LOW;
-+
-+			if (!of_property_read_u32(cnp, "gpio-export,output", &val))
-+				flags |= val ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
-+			else
-+				flags |= GPIOF_IN;
-+
-+			if (devm_gpio_request_one(&pdev->dev, gpio, flags, name ? name : of_node_full_name(np)))
-+				continue;
-+
-+			dmc = of_property_read_bool(cnp, "gpio-export,direction_may_change");
-+			gpio_export_with_name(gpio, dmc, name);
-+			nb++;
-+		}
-+	}
-+
-+	dev_info(&pdev->dev, "%d gpio(s) exported\n", nb);
-+
-+	return 0;
-+}
-+
-+static struct platform_driver gpio_export_driver = {
-+	.driver		= {
-+		.name		= "gpio-export",
-+		.owner	= THIS_MODULE,
-+		.of_match_table	= of_match_ptr(gpio_export_ids),
-+	},
-+	.probe		= of_gpio_export_probe,
-+};
-+
-+module_platform_driver(gpio_export_driver);
-+
-+#endif
---- a/include/asm-generic/gpio.h
-+++ b/include/asm-generic/gpio.h
-@@ -127,6 +127,12 @@ static inline int gpio_export(unsigned g
- 	return gpiod_export(gpio_to_desc(gpio), direction_may_change);
- }
- 
-+int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name);
-+static inline int gpio_export_with_name(unsigned gpio, bool direction_may_change, const char *name)
-+{
-+	return __gpiod_export(gpio_to_desc(gpio), direction_may_change, name);
-+}
-+
- static inline int gpio_export_link(struct device *dev, const char *name,
- 				   unsigned gpio)
- {
---- a/include/linux/gpio/consumer.h
-+++ b/include/linux/gpio/consumer.h
-@@ -668,6 +668,7 @@ static inline void devm_acpi_dev_remove_
- 
- #if IS_ENABLED(CONFIG_GPIOLIB) && IS_ENABLED(CONFIG_GPIO_SYSFS)
- 
-+int _gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name);
- int gpiod_export(struct gpio_desc *desc, bool direction_may_change);
- int gpiod_export_link(struct device *dev, const char *name,
- 		      struct gpio_desc *desc);
-@@ -675,6 +676,13 @@ void gpiod_unexport(struct gpio_desc *de
- 
- #else  /* CONFIG_GPIOLIB && CONFIG_GPIO_SYSFS */
- 
-+static inline int _gpiod_export(struct gpio_desc *desc,
-+			       bool direction_may_change,
-+			       const char *name)
-+{
-+	return -ENOSYS;
-+}
-+
- static inline int gpiod_export(struct gpio_desc *desc,
- 			       bool direction_may_change)
- {
---- a/drivers/gpio/gpiolib-sysfs.c
-+++ b/drivers/gpio/gpiolib-sysfs.c
-@@ -571,7 +571,7 @@ static struct class gpio_class = {
-  *
-  * Returns zero on success, else an error.
-  */
--int gpiod_export(struct gpio_desc *desc, bool direction_may_change)
-+int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name)
- {
- 	struct gpio_chip	*chip;
- 	struct gpio_device	*gdev;
-@@ -633,6 +633,8 @@ int gpiod_export(struct gpio_desc *desc,
- 	offset = gpio_chip_hwgpio(desc);
- 	if (chip->names && chip->names[offset])
- 		ioname = chip->names[offset];
-+	if (name)
-+		ioname = name;
- 
- 	dev = device_create_with_groups(&gpio_class, &gdev->dev,
- 					MKDEV(0, 0), data, gpio_groups,
-@@ -654,6 +656,12 @@ err_unlock:
- 	gpiod_dbg(desc, "%s: status %d\n", __func__, status);
- 	return status;
- }
-+EXPORT_SYMBOL_GPL(__gpiod_export);
-+
-+int gpiod_export(struct gpio_desc *desc, bool direction_may_change)
-+{
-+	return __gpiod_export(desc, direction_may_change, NULL);
-+}
- EXPORT_SYMBOL_GPL(gpiod_export);
- 
- static int match_export(struct device *dev, const void *desc)

target/linux/lantiq/patches-5.4/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch

-From f8c5db89e793a4bc6c1e87bd7b3a5cec16b75bc3 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Wed, 10 Sep 2014 22:42:14 +0200
-Subject: [PATCH 35/36] owrt: lantiq: wifi and ethernet eeprom handling
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |   3 +
- arch/mips/lantiq/xway/Makefile                     |   3 +
- arch/mips/lantiq/xway/ath5k_eep.c                  | 136 +++++++++++++++++++++
- arch/mips/lantiq/xway/eth_mac.c                    |  25 ++++
- drivers/net/ethernet/lantiq_etop.c                 |   6 +-
- 5 files changed, 172 insertions(+), 1 deletion(-)
- create mode 100644 arch/mips/lantiq/xway/ath5k_eep.c
- create mode 100644 arch/mips/lantiq/xway/eth_mac.c
-
---- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
-+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
-@@ -102,5 +102,8 @@ int xrx200_gphy_boot(struct device *dev,
- extern void ltq_pmu_enable(unsigned int module);
- extern void ltq_pmu_disable(unsigned int module);
- 
-+/* allow the ethernet driver to load a flash mapped mac addr */
-+const u8* ltq_get_eth_mac(void);
-+
- #endif /* CONFIG_SOC_TYPE_XWAY */
- #endif /* _LTQ_XWAY_H__ */
---- a/arch/mips/lantiq/xway/Makefile
-+++ b/arch/mips/lantiq/xway/Makefile
-@@ -8,3 +8,6 @@ obj-y += timer.o
- endif
- 
- obj-y += vmmc.o
-+
-+obj-y += eth_mac.o
-+obj-$(CONFIG_PCI) += ath5k_eep.o
---- /dev/null
-+++ b/arch/mips/lantiq/xway/ath5k_eep.c
-@@ -0,0 +1,136 @@
-+/*
-+ *  Copyright (C) 2011 Luca Olivetti <luca@ventoso.org>
-+ *  Copyright (C) 2011 John Crispin <blogic@openwrt.org>
-+ *  Copyright (C) 2011 Andrej Vlašić <andrej.vlasic0@gmail.com>
-+ *  Copyright (C) 2013 Álvaro Fernández Rojas <noltari@gmail.com>
-+ *  Copyright (C) 2013 Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
-+ *  Copyright (C) 2015 Vittorio Gambaletta <openwrt@vittgam.net>
-+ *
-+ *  This program is free software; you can redistribute it and/or modify it
-+ *  under the terms of the GNU General Public License version 2 as published
-+ *  by the Free Software Foundation.
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/platform_device.h>
-+#include <linux/etherdevice.h>
-+#include <linux/ath5k_platform.h>
-+#include <linux/pci.h>
-+#include <linux/err.h>
-+#include <linux/mtd/mtd.h>
-+#include <lantiq_soc.h>
-+
-+extern int (*ltq_pci_plat_dev_init)(struct pci_dev *dev);
-+struct ath5k_platform_data ath5k_pdata;
-+static u8 athxk_eeprom_mac[6];
-+
-+static int ath5k_pci_plat_dev_init(struct pci_dev *dev)
-+{
-+	dev->dev.platform_data = &ath5k_pdata;
-+	return 0;
-+}
-+
-+static int ath5k_eep_load;
-+int __init of_ath5k_eeprom_probe(struct platform_device *pdev)
-+{
-+	struct device_node *np = pdev->dev.of_node, *mtd_np = NULL;
-+	int mac_offset;
-+	u32 mac_inc = 0;
-+	int i;
-+	struct mtd_info *the_mtd;
-+	size_t flash_readlen;
-+	const __be32 *list;
-+	const char *part;
-+	phandle phandle;
-+
-+	list = of_get_property(np, "ath,eep-flash", &i);
-+	if (!list || (i != (2 * sizeof(*list))))
-+		return -ENODEV;
-+
-+	phandle = be32_to_cpup(list++);
-+	if (phandle)
-+		mtd_np = of_find_node_by_phandle(phandle);
-+
-+	if (!mtd_np)
-+		return -ENODEV;
-+
-+	part = of_get_property(mtd_np, "label", NULL);
-+	if (!part)
-+		part = mtd_np->name;
-+
-+	the_mtd = get_mtd_device_nm(part);
-+	if (IS_ERR(the_mtd))
-+		return -ENODEV;
-+
-+	ath5k_pdata.eeprom_data = kmalloc(ATH5K_PLAT_EEP_MAX_WORDS<<1, GFP_KERNEL);
-+
-+	i = mtd_read(the_mtd, be32_to_cpup(list), ATH5K_PLAT_EEP_MAX_WORDS << 1,
-+		&flash_readlen, (void *) ath5k_pdata.eeprom_data);
-+
-+	if (!of_property_read_u32(np, "ath,mac-offset", &mac_offset)) {
-+		size_t mac_readlen;
-+		mtd_read(the_mtd, mac_offset, 6, &mac_readlen,
-+			(void *) athxk_eeprom_mac);
-+	}
-+	put_mtd_device(the_mtd);
-+
-+	if (((ATH5K_PLAT_EEP_MAX_WORDS<<1) != flash_readlen) || i) {
-+		dev_err(&pdev->dev, "failed to load eeprom from mtd\n");
-+		return -ENODEV;
-+	}
-+
-+	if (of_find_property(np, "ath,eep-swap", NULL))
-+		for (i = 0; i < ATH5K_PLAT_EEP_MAX_WORDS; i++)
-+			ath5k_pdata.eeprom_data[i] = swab16(ath5k_pdata.eeprom_data[i]);
-+
-+	if (!is_valid_ether_addr(athxk_eeprom_mac) && ltq_get_eth_mac())
-+		ether_addr_copy(athxk_eeprom_mac, ltq_get_eth_mac());
-+
-+	if (!is_valid_ether_addr(athxk_eeprom_mac)) {
-+		dev_warn(&pdev->dev, "using random mac\n");
-+		random_ether_addr(athxk_eeprom_mac);
-+	}
-+
-+	if (!of_property_read_u32(np, "ath,mac-increment", &mac_inc))
-+		athxk_eeprom_mac[5] += mac_inc;
-+
-+	ath5k_pdata.macaddr = athxk_eeprom_mac;
-+	ltq_pci_plat_dev_init = ath5k_pci_plat_dev_init;
-+
-+	dev_info(&pdev->dev, "loaded ath5k eeprom\n");
-+
-+	return 0;
-+}
-+
-+static struct of_device_id ath5k_eeprom_ids[] = {
-+	{ .compatible = "ath5k,eeprom" },
-+	{ }
-+};
-+
-+static struct platform_driver ath5k_eeprom_driver = {
-+	.driver		= {
-+		.name		= "ath5k,eeprom",
-+		.owner	= THIS_MODULE,
-+		.of_match_table	= of_match_ptr(ath5k_eeprom_ids),
-+	},
-+};
-+
-+static int __init of_ath5k_eeprom_init(void)
-+{
-+	int ret = platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe);
-+
-+	if (ret)
-+		ath5k_eep_load = 1;
-+
-+	return ret;
-+}
-+
-+static int __init of_ath5k_eeprom_init_late(void)
-+{
-+	if (!ath5k_eep_load)
-+		return 0;
-+
-+	return platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe);
-+}
-+late_initcall(of_ath5k_eeprom_init_late);
-+subsys_initcall(of_ath5k_eeprom_init);
---- /dev/null
-+++ b/arch/mips/lantiq/xway/eth_mac.c
-@@ -0,0 +1,25 @@
-+/*
-+ *  Copyright (C) 2012 John Crispin <blogic@openwrt.org>
-+ *
-+ *  This program is free software; you can redistribute it and/or modify it
-+ *  under the terms of the GNU General Public License version 2 as published
-+ *  by the Free Software Foundation.
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/if_ether.h>
-+
-+static u8 eth_mac[6];
-+static int eth_mac_set;
-+
-+const u8* ltq_get_eth_mac(void)
-+{
-+	return eth_mac;
-+}
-+
-+static int __init setup_ethaddr(char *str)
-+{
-+	eth_mac_set = mac_pton(str, eth_mac);
-+	return !eth_mac_set;
-+}
-+early_param("ethaddr", setup_ethaddr);
---- a/drivers/net/ethernet/lantiq_etop.c
-+++ b/drivers/net/ethernet/lantiq_etop.c
-@@ -764,7 +764,11 @@ ltq_etop_init(struct net_device *dev)
- 	if (err)
- 		goto err_hw;
- 
--	memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
-+	memcpy(&mac.sa_data, ltq_get_eth_mac(), ETH_ALEN);
-+
-+	if (priv->mac && !is_valid_ether_addr(mac.sa_data))
-+		memcpy(&mac.sa_data, priv->mac, ETH_ALEN);
-+
- 	if (!is_valid_ether_addr(mac.sa_data)) {
- 		pr_warn("etop: invalid MAC, using random\n");
- 		eth_random_addr(mac.sa_data);

target/linux/lantiq/patches-5.4/0042-arch-mips-increase-io_space_limit.patch

-From 9807eb80a1b3bad7a4a89aa6566497bb1cadd6ef Mon Sep 17 00:00:00 2001
-From: John Crispin <john@phrozen.org>
-Date: Fri, 3 Jun 2016 13:12:20 +0200
-Subject: [PATCH] arch: mips: increase io_space_limit
-
-this value comes from x86 and breaks some pci devices
-
-Signed-off-by: John Crispin <john@phrozen.org>
----
- arch/mips/include/asm/io.h |    2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/mips/include/asm/io.h
-+++ b/arch/mips/include/asm/io.h
-@@ -53,7 +53,7 @@
- 
- /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
- 
--#define IO_SPACE_LIMIT 0xffff
-+#define IO_SPACE_LIMIT 0xffffffff
- 
- /*
-  * On MIPS I/O ports are memory mapped, so we access them using normal

target/linux/lantiq/patches-5.4/0050-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch

-From de2cad82c4d0872066f83ce59462603852b47f03 Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Fri, 6 Jan 2017 17:55:24 +0100
-Subject: [PATCH 2/2] usb: dwc2:  add support for other Lantiq SoCs
-
-The size of the internal RAM of the DesignWare USB controller changed
-between the different Lantiq SoCs. We have the following sizes:
-
-Amazon + Danube: 8 KByte
-Amazon SE + arx100: 2 KByte
-xrx200 + xrx300: 2.5 KByte
-
-For Danube SoC we do not provide the params and let the driver decide
-to use sane defaults, for the Amazon SE and arx100 we use small fifos
-and for the xrx200 and xrx300 SCs a little bit bigger periodic fifo.
-The auto detection of max_transfer_size and max_packet_count should
-work, so remove it.
-
-Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
----
- drivers/usb/dwc2/platform.c | 46 ++++++++++++++++++++++++++++++++++++++-------
- 1 file changed, 39 insertions(+), 7 deletions(-)
-
---- a/drivers/usb/dwc2/params.c
-+++ b/drivers/usb/dwc2/params.c
-@@ -92,7 +92,14 @@ static void dwc2_set_rk_params(struct dw
- 	p->power_down = 0;
- }
- 
--static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg)
-+static void dwc2_set_ltq_danube_params(struct dwc2_hsotg *hsotg)
-+{
-+	struct dwc2_core_params *p = &hsotg->params;
-+
-+	p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
-+}
-+
-+static void dwc2_set_ltq_ase_params(struct dwc2_hsotg *hsotg)
- {
- 	struct dwc2_core_params *p = &hsotg->params;
- 
-@@ -100,12 +107,20 @@ static void dwc2_set_ltq_params(struct d
- 	p->host_rx_fifo_size = 288;
- 	p->host_nperio_tx_fifo_size = 128;
- 	p->host_perio_tx_fifo_size = 96;
--	p->max_transfer_size = 65535;
--	p->max_packet_count = 511;
- 	p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
- 		GAHBCFG_HBSTLEN_SHIFT;
- }
- 
-+static void dwc2_set_ltq_xrx200_params(struct dwc2_hsotg *hsotg)
-+{
-+	struct dwc2_core_params *p = &hsotg->params;
-+
-+	p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
-+	p->host_rx_fifo_size = 288;
-+	p->host_nperio_tx_fifo_size = 128;
-+	p->host_perio_tx_fifo_size = 136;
-+}
-+
- static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg)
- {
- 	struct dwc2_core_params *p = &hsotg->params;
-@@ -167,8 +182,11 @@ const struct of_device_id dwc2_of_match_
- 	{ .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
- 	{ .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params  },
- 	{ .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params },
--	{ .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params },
--	{ .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params },
-+	{ .compatible = "lantiq,danube-usb", .data = &dwc2_set_ltq_danube_params },
-+	{ .compatible = "lantiq,ase-usb", .data = &dwc2_set_ltq_ase_params },
-+	{ .compatible = "lantiq,arx100-usb", .data = &dwc2_set_ltq_ase_params },
-+	{ .compatible = "lantiq,xrx200-usb", .data = &dwc2_set_ltq_xrx200_params },
-+	{ .compatible = "lantiq,xrx300-usb", .data = &dwc2_set_ltq_xrx200_params },
- 	{ .compatible = "snps,dwc2" },
- 	{ .compatible = "samsung,s3c6400-hsotg",
- 	  .data = dwc2_set_s3c6400_params },

target/linux/lantiq/patches-5.4/0051-MIPS-lantiq-improve-USB-initialization.patch

-From 14909c4e4e836925668e74fc6e0e85ba0283cbf9 Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Fri, 6 Jan 2017 17:40:12 +0100
-Subject: [PATCH 2/2] MIPS: lantiq: improve USB initialization
-
-This adds code to initialize the USB controller and PHY also on Danube,
-Amazon SE and AR10. This code is based on the Vendor driver from
-different UGW versions and compared to the hardware documentation.
-
-Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
----
- arch/mips/lantiq/xway/sysctrl.c |  20 +++++++
- 2 files changed, 110 insertions(+), 30 deletions(-)
-
-
---- a/arch/mips/lantiq/xway/sysctrl.c
-+++ b/arch/mips/lantiq/xway/sysctrl.c
-@@ -244,6 +244,25 @@ static void pmu_disable(struct clk *clk)
- 		pr_warn("deactivating PMU module failed!");
- }
- 
-+static void usb_set_clock(void)
-+{
-+	unsigned int val = ltq_cgu_r32(ifccr);
-+
-+	if (of_machine_is_compatible("lantiq,ar10") ||
-+	    of_machine_is_compatible("lantiq,grx390")) {
-+		val &= ~0x03; /* XTAL divided by 3 */
-+	} else if (of_machine_is_compatible("lantiq,ar9") ||
-+		   of_machine_is_compatible("lantiq,vr9")) {
-+		/* TODO: this depends on the XTAL frequency */
-+		val |= 0x03; /* XTAL divided by 3 */
-+	} else if (of_machine_is_compatible("lantiq,ase")) {
-+		val |= 0x20; /* from XTAL */
-+	} else if (of_machine_is_compatible("lantiq,danube")) {
-+		val |= 0x30; /* 12 MHz, generated from 36 MHz */
-+	}
-+	ltq_cgu_w32(val, ifccr);
-+}
-+
- /* the pci enable helper */
- static int pci_enable(struct clk *clk)
- {
-@@ -565,4 +584,5 @@ void __init ltq_soc_init(void)
- 		clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
- 		clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
- 	}
-+	usb_set_clock();
- }

target/linux/lantiq/patches-5.4/0101-find_active_root.patch

---- a/drivers/mtd/parsers/ofpart_core.c
-+++ b/drivers/mtd/parsers/ofpart_core.c
-@@ -38,6 +38,38 @@ static bool node_has_compatible(struct d
- 	return of_get_property(pp, "compatible", NULL);
- }
- 
-+static uint8_t * brnboot_get_selected_root_part(struct mtd_info *master,
-+						loff_t offset)
-+{
-+	static uint8_t root_id;
-+	int err, len;
-+
-+	err = mtd_read(master, offset, 0x01, &len, &root_id);
-+
-+	if (mtd_is_bitflip(err) || !err)
-+		return &root_id;
-+
-+	return NULL;
-+}
-+
-+static void brnboot_set_active_root_part(struct mtd_partition *pparts,
-+					 struct device_node **part_nodes,
-+					 int nr_parts,
-+					 uint8_t *root_id)
-+{
-+	int i;
-+
-+	for (i = 0; i < nr_parts; i++) {
-+		int part_root_id;
-+
-+		if (!of_property_read_u32(part_nodes[i], "brnboot,root-id", &part_root_id)
-+		    && part_root_id == *root_id) {
-+			pparts[i].name = "firmware";
-+			break;
-+		}
-+	}
-+}
-+
- static int parse_fixed_partitions(struct mtd_info *master,
- 				  const struct mtd_partition **pparts,
- 				  struct mtd_part_parser_data *data)
-@@ -51,6 +83,8 @@ static int parse_fixed_partitions(struct
- 	struct device_node *pp;
- 	int nr_parts, i, ret = 0;
- 	bool dedicated = true;
-+	uint8_t *proot_id = NULL;
-+	struct device_node **part_nodes;
- 
- 	/* Pull of_node from the master device node */
- 	mtd_node = mtd_get_of_node(master);
-@@ -95,7 +129,9 @@ static int parse_fixed_partitions(struct
- 		return 0;
- 
- 	parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL);
--	if (!parts)
-+	part_nodes = kcalloc(nr_parts, sizeof(*part_nodes), GFP_KERNEL);
-+
-+	if (!parts || !part_nodes)
- 		return -ENOMEM;
- 
- 	i = 0;
-@@ -144,6 +180,11 @@ static int parse_fixed_partitions(struct
- 		if (of_get_property(pp, "lock", &len))
- 			parts[i].mask_flags |= MTD_POWERUP_LOCK;
- 
-+		if (!proot_id && of_device_is_compatible(pp, "brnboot,root-selector"))
-+			proot_id = brnboot_get_selected_root_part(master, parts[i].offset);
-+
-+		part_nodes[i] = pp;
-+
- 		i++;
- 	}
- 
-@@ -153,6 +194,11 @@ static int parse_fixed_partitions(struct
- 	if (quirks && quirks->post_parse)
- 		quirks->post_parse(master, parts, nr_parts);
- 
-+	if (proot_id)
-+		brnboot_set_active_root_part(parts, part_nodes, nr_parts, proot_id);
-+
-+	kfree(part_nodes);
-+
- 	*pparts = parts;
- 	return nr_parts;
- 
-@@ -163,6 +209,7 @@ ofpart_fail:
- ofpart_none:
- 	of_node_put(pp);
- 	kfree(parts);
-+	kfree(part_nodes);
- 	return ret;
- }
- 

target/linux/lantiq/patches-5.4/0110-MIPS-lantiq-dma-add-small-delay-after-reset.patch

-From 497acc03cd3918baabe25d46e30c5c62b998e24d Mon Sep 17 00:00:00 2001
-From: Aleksander Jan Bajkowski <olek2@wp.pl>
-Date: Sat, 19 Jun 2021 13:38:12 +0200
-Subject: [PATCH 1/5] MIPS: lantiq: dma: add small delay after reset
-
-Reading the DMA registers immediately after the reset causes
-Data Bus Error. Adding a small delay fixes this problem.
-
-Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
----
- arch/mips/lantiq/xway/dma.c | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/arch/mips/lantiq/xway/dma.c
-+++ b/arch/mips/lantiq/xway/dma.c
-@@ -11,6 +11,7 @@
- #include <linux/export.h>
- #include <linux/spinlock.h>
- #include <linux/clk.h>
-+#include <linux/delay.h>
- #include <linux/err.h>
- 
- #include <lantiq_soc.h>
-@@ -221,6 +222,8 @@ ltq_dma_init(struct platform_device *pde
- 	clk_enable(clk);
- 	ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL);
- 
-+	usleep_range(1, 10);
-+
- 	/* disable all interrupts */
- 	ltq_dma_w32(0, LTQ_DMA_IRNEN);
- 

target/linux/lantiq/patches-5.4/0111-MIPS-lantiq-dma-reset-correct-number-of-channel.patch

-From d31260c2f6a5cdddb052ab7cb09560eb23ce6597 Mon Sep 17 00:00:00 2001
-From: Aleksander Jan Bajkowski <olek2@wp.pl>
-Date: Thu, 15 Apr 2021 21:28:24 +0200
-Subject: [PATCH 2/5] MIPS: lantiq: dma: reset correct number of channel
-
-Different SoCs have a different number of channels, e.g .:
-* amazon-se has 10 channels,
-* danube+ar9 have 20 channels,
-* vr9 has 28 channels,
-* ar10 has 24 channels.
-
-We can read the ID register and, depending on the reported
-number of channels, reset the appropriate number of channels.
-
-Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
----
- arch/mips/lantiq/xway/dma.c | 11 ++++++-----
- 1 file changed, 6 insertions(+), 5 deletions(-)
-
---- a/arch/mips/lantiq/xway/dma.c
-+++ b/arch/mips/lantiq/xway/dma.c
-@@ -30,6 +30,7 @@
- #define LTQ_DMA_PCTRL		0x44
- #define LTQ_DMA_IRNEN		0xf4
- 
-+#define DMA_ID_CHNR		GENMASK(26, 20)	/* channel number */
- #define DMA_DESCPT		BIT(3)		/* descriptor complete irq */
- #define DMA_TX			BIT(8)		/* TX channel direction */
- #define DMA_CHAN_ON		BIT(0)		/* channel on / off bit */
-@@ -40,7 +41,6 @@
- #define DMA_POLL		BIT(31)		/* turn on channel polling */
- #define DMA_CLK_DIV4		BIT(6)		/* polling clock divider */
- #define DMA_2W_BURST		BIT(1)		/* 2 word burst length */
--#define DMA_MAX_CHANNEL		20		/* the soc has 20 channels */
- #define DMA_ETOP_ENDIANNESS	(0xf << 8) /* endianness swap etop channels */
- #define DMA_WEIGHT	(BIT(17) | BIT(16))	/* default channel wheight */
- 
-@@ -206,7 +206,7 @@ ltq_dma_init(struct platform_device *pde
- {
- 	struct clk *clk;
- 	struct resource *res;
--	unsigned id;
-+	unsigned int id, nchannels;
- 	int i;
- 
- 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-@@ -228,17 +228,18 @@ ltq_dma_init(struct platform_device *pde
- 	ltq_dma_w32(0, LTQ_DMA_IRNEN);
- 
- 	/* reset/configure each channel */
--	for (i = 0; i < DMA_MAX_CHANNEL; i++) {
-+	id = ltq_dma_r32(LTQ_DMA_ID);
-+	nchannels = ((id & DMA_ID_CHNR) >> 20);
-+	for (i = 0; i < nchannels; i++) {
- 		ltq_dma_w32(i, LTQ_DMA_CS);
- 		ltq_dma_w32(DMA_CHAN_RST, LTQ_DMA_CCTRL);
- 		ltq_dma_w32(DMA_POLL | DMA_CLK_DIV4, LTQ_DMA_CPOLL);
- 		ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
- 	}
- 
--	id = ltq_dma_r32(LTQ_DMA_ID);
- 	dev_info(&pdev->dev,
- 		"Init done - hw rev: %X, ports: %d, channels: %d\n",
--		id & 0x1f, (id >> 16) & 0xf, id >> 20);
-+		id & 0x1f, (id >> 16) & 0xf, nchannels);
- 
- 	return 0;
- }