init commit

.gitignore

+/target
+/.vscode
+a.out

Cargo.lock

+# This file is automatically @generated by Cargo.
+# It is not intended for manual editing.
+version = 3
+
+[[package]]
+name = "bitflags"
+version = "1.3.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "bef38d45163c2f1dde094a7dfd33ccf595c92905c8f8f4fdc18d06fb1037718a"
+
+[[package]]
+name = "cfg-if"
+version = "1.0.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "baf1de4339761588bc0619e3cbc0120ee582ebb74b53b4efbf79117bd2da40fd"
+
+[[package]]
+name = "elf"
+version = "0.7.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "6de42b0529467fc9a2692fd91585c84dd255fb15b0df0f80299724a9456986c6"
+
+[[package]]
+name = "elfloader"
+version = "0.16.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "6a7b18d35bf8ec3bac59c3ec29cf1f1b46e764e00b42a9c0c754d06e38e78f3b"
+dependencies = [
+ "bitflags",
+ "log",
+ "xmas-elf",
+]
+
+[[package]]
+name = "log"
+version = "0.4.17"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "abb12e687cfb44aa40f41fc3978ef76448f9b6038cad6aef4259d3c095a2382e"
+dependencies = [
+ "cfg-if",
+]
+
+[[package]]
+name = "riscv-emu"
+version = "0.1.0"
+dependencies = [
+ "elf",
+ "elfloader",
+]
+
+[[package]]
+name = "xmas-elf"
+version = "0.8.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "8d29b4d8e7beaceb4e77447ba941a7600d23d0319ab52da0461abea214832d5a"
+dependencies = [
+ "zero",
+]
+
+[[package]]
+name = "zero"
+version = "0.1.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "5f1bc8a6b2005884962297587045002d8cfb8dcec9db332f4ca216ddc5de82c5"

Cargo.toml

+[package]
+name = "riscv-emu"
+version = "0.1.0"
+edition = "2021"
+
+# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
+
+[dependencies]
+elf = "0.7.0"
+elfloader = "0.16.0"

asmcode.s

+addi sp, zero, 40                   #init stack
+
+beq x0, x0, main                    #start in main
+
+fib:
+    addi t2, zero, 0
+	beq a0, t2, fibJump             #retrun if n = 0
+	addi t2, zero, 1
+	beq a0, t2, fibJump             #retrun if n = 1
+    addi t1, zero, 2
+	beq a0, t1, fibJump             #retrun if n = 2
+
+	addi a0, a0, -1                 #n = n -1
+
+	addi sp, sp, -4                 #go to next free addr
+	sw t0, 0(sp)                    #save the current result
+    		
+	addi sp, sp, -4                 #go to next free addr
+	sw a0, 0(sp)                    #save the tmp value
+				
+	jal t0, fib                     #start the recursion for n-1
+
+	add t1, zero, a0                #save current n value to a tmp register
+	lw a0, 0(sp)		            #load old n-value
+
+	addi a0, a0, -1                 #n = n -1
+
+	sw t1, 0(sp)                    #save current n value to mem
+
+	jal t0, fib                     #start the recursion for n-2
+	
+	lw t1, 0(sp)                    #load the tmp value from n-1
+	
+    addi sp, sp, 4                  #go to last addr
+
+	add t2, a0, t1                  #add up n-1 and n-2
+	lw t0, 0(sp)                    #load the last val
+	addi sp, sp, 4		            #reset stack
+
+fibJump:                 	
+    add a0, zero, t2                #save the result to a0
+    jalr x0, t0 ,0
+
+main:
+    addi a0, zero, 7                #<-- set input number
+    jal t0, fib
+
+endLoop:                            #inf loop
+beq x0, x0 , endLoop

src/main.rs

+#![feature(read_buf)]
+#![allow(warnings)]
+use std;
+use std::env;
+use std::io::Read;
+use std::process::exit;
+use std::fs;
+use std::io;
+use elf;
+use elf::ElfBytes;
+use elf::endian::AnyEndian;
+use elf::hash::sysv_hash;
+use elf::note::Note;
+use elf::note::NoteGnuBuildId;
+use elf::section::SectionHeader;
+use elf::file::FileHeader;
+use elf::file::Class;
+use elfloader::*;
+use std::collections::HashMap;
+
+
+type Immediate = i32;
+
+
+struct Machine {
+    mem: Vec<u8>,
+    registers: [i32;32],
+    pc: u32,
+}
+
+impl Machine {
+    fn new(memsize: usize) -> Self {
+        Machine {
+            mem: Vec::with_capacity(memsize * 1024),
+            registers: [0;32],
+            pc: 0,
+        }
+    }
+
+    fn start(&mut self) {
+        let b = self.fetch();
+
+        let i = Instruction::decode(b);
+
+        self.pc += 1;
+    }
+
+    fn fetch(&mut self) -> [u8;4] {
+        [
+            self.mem[self.pc as usize],
+            self.mem[(self.pc + 1) as usize],
+            self.mem[(self.pc + 2) as usize],
+            self.mem[(self.pc + 3) as usize],
+        ]
+    }
+}
+
+
+#[derive(Debug)]
+
+enum Register {
+    x0(u32),
+    x1(u32),
+    x2(u32),
+    x3(u32),
+    x4(u32),
+    x5(u32),
+    x6(u32),
+    x7(u32),
+    x8(u32),
+    x9(u32),
+    x10(u32),
+    x11(u32),
+    x12(u32),
+    x13(u32),
+    x14(u32),
+    x15(u32),
+    x16(u32),
+    x17(u32),
+    x18(u32),
+    x19(u32),
+    x20(u32),
+    x21(u32),
+    x22(u32),
+    x23(u32),
+    x24(u32),
+    x25(u32),
+    x26(u32),
+    x27(u32),
+    x28(u32),
+    x29(u32),
+    x30(u32),
+    x31(u32),
+    x32(u32),
+}
+
+
+#[derive(Debug)]
+enum Instruction {
+    // Load Instructions
+    LB(Register, Register, i32),
+    LH(Register, Register, i32),
+    LW(Register, Register, i32),
+    LBU(Register, Register, i32),
+    LHU(Register, Register, i32),
+
+    // Store Instructions
+    SB(Register, Register, i32),
+    SH(Register, Register, i32),
+    SW(Register, Register, i32),
+
+    // Shift istructions
+    SL(Register, Register, Register),
+    SLLI(Register, Register, i32),
+    SRL(Register, Register, Register),
+    SRLI(Register, Register, i32),
+    SRA(Register, Register, Register),
+    SRAI(Register, Register, i32),
+
+    // Arithmetic
+    ADD(Register, Register, Register),
+    ADDI(Register, Register, i32),
+    SUB(Register, Register, Register),
+    LUI(Register, i32),
+    AUIPC(Register, i32),
+
+    // Logical
+    SLT(Register, Register, Register),
+    SLTI(Register, Register, i32),
+    SLTU(Register, Register, Register),
+    SLTIU(Register, Register, i32),
+
+    // Branching
+    BEQ(Register, Register, i32),
+    BNE(Register, Register, i32),
+    BLT(Register, Register, i32),
+    BGE(Register, Register, i32),
+    BLTU(Register, Register, i32),
+    BGEU(Register, Register, i32),
+
+    // jumps
+    JAL(Register, Immediate),
+    JALR(Register, Register, Immediate),
+
+    // System
+}
+
+impl Instruction {
+    fn decode(instr: [u8;4]) -> Self {
+        let b = u32::from_le_bytes(instr);
+        let opcode = b & 0b01111111;
+        let reg_rd = (b >> 6) & 0b00011111;
+
+        match opcode {
+            // 0b0010011 => Self::ADDI(0, 0, 0),
+            _ => unimplemented!("the opcode {:b} is not implemented", opcode)
+        }
+    }
+}
+
+
+
+fn main() {
+    if env::args().len() != 2 {
+        eprintln!("no args given");
+        exit(1);
+    }
+
+    let path = std::path::PathBuf::from(env::args().next().unwrap());
+    let file_data = std::fs::read(path).expect("Could not read file.");
+
+    let slice = file_data.as_slice();
+
+
+    let elfheader = FileHeader::parse_tail((AnyEndian::Little, Class::ELF32, 0x0, 0), slice).unwrap();
+
+    println!("loading elf binary");
+    println!("entry point: {:x}", elfheader.e_entry);
+    println!("{:#?}", elfheader);
+
+    let elf = ElfBytes::<AnyEndian>::minimal_parse(slice).unwrap();
+    let text_header = elf.section_header_by_name(".text").unwrap().unwrap();
+    let data = elf.section_data(&text_header).unwrap().0;
+
+    let section_headers = elf.section_headers_with_strtab().unwrap().1.unwrap();
+
+
+    let (shdrs_opt, strtab_opt) = elf
+        .section_headers_with_strtab()
+        .expect("shdrs offsets should be valid");
+    let (shdrs, strtab) = (
+        shdrs_opt.expect("Should have shdrs"),
+        strtab_opt.expect("Should have strtab")
+    );
+
+    // Parse the shdrs and collect them into a map keyed on their zero-copied name
+    let with_names: HashMap<&str, (SectionHeader, Vec<u8>)> = shdrs
+        .iter()
+        .map(|shdr| {(
+            strtab.get(shdr.sh_name as usize).expect("Failed to get section name"),
+            (shdr, Vec::from(elf.section_data(&shdr).unwrap().0))
+        )})
+        .collect();
+
+
+    let text = with_names.get(".text").unwrap();
+
+
+
+    // println!("{:#?}", with_names);
+
+    let mut machine = Machine::new(1024);
+
+    for i in text.1.bytes() {
+        println!("{:x}", i.unwrap());
+        // machine.mem.push(i.unwrap());
+    }
+
+    // machine.start();
+
+    // let mut buf: [u8;4] = [0, 0, 0, 0];
+
+    // f.read_to_end(&mut machine.mem).unwrap();
+
+    // machine.start();
+
+    // sum += buf[0] as u32;
+    // sum += (buf[1] as u32) <<8 as u32;
+    // sum += (buf[2] as u32) <<16 as u32;
+    // sum += (buf[3] as u32) <<24 as u32;
+
+    // println!("{:08b} {:08b} {:08b} {:08b} {:#010x}", buf[3], buf[2], buf[1], buf[0], sum)
+    //println!("{:034b}", buf[0])
+
+}
+
+
+
+// mod tests {
+//     use crate::*;
+//     #[test]
+//     fn test_4byte_to_32bit_conv() {
+//         assert_eq!(bytes_to_u32([0,0,0,42]), 42)
+//     }
+// }