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Commit cfb8f85e authored by Leo's avatar Leo :shark:
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cleanup

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Makefile
+ 5
− 14
View file @ cfb8f85e
filename = top
pcf_file = io.pcf
icesprog = ~/projects/icesugar/tools/icesprog.x64.linux
build:
$(filename).bin:
yosys -qp "synth_ice40 -json $(filename).json" $(filename).v
nextpnr-ice40 -q\
-l pnr.log \
--up5k \
--pcf-allow-unconstrained \
--package sg48 \
--json $(filename).json \
--pcf $(pcf_file) \
--asc $(filename).asc
icepack $(filename).asc $(filename).bin
# head -n -434 pnr.log | tail -18
#prog: #for sram
#iceprog -S $(filename).bin
#prog_flash:
# @if [ -d '$(ICELINK_DIR)' ]; \
# then \
# cp $(filename).bin $(ICELINK_DIR); \
# else \
# echo "iCELink not found"; \
# exit 1; \
# fi
flash: build
~/projects/icesugar/tools/icesprog.x64.linux $(filename).bin
flash: $(filename).bin
$(icesprog) $(filename).bin
clean:
rm -rf $(filename).blif $(filename).asc $(filename).bin
Readme.md
+ 1
− 0
View file @ cfb8f85e
iverilog -o icarusTest top.v && vvp icarusTest
GDK_BACKEND=x11 gtkwave
alu.v
+ 4
− 5
View file @ cfb8f85e
......@@ -52,15 +52,14 @@ module alu(
assign zeroFlag = zeroFlagReg;
assign carryFlag = carryFlagReg;
always @ (posedge clr) begin
zeroFlagReg <= 0;
carryFlagReg <= 0;
end
always @ (posedge clk) begin
always @ (posedge clk) begin // TODO nicht richtiger trigger
if (wrFlags) begin
zeroFlagReg <= (busIn == 0) ? 1'b1 : 1'b0;
carryFlagReg <= (aVal + bVal > 15'b111111111111111) ? 1'b1 : 1'b0;
end else if (clr) begin
zeroFlagReg <= 0;
carryFlagReg <= 0;
end
end
......
control.mem
+ 28
− 28
View file @ cfb8f85e
0210
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0044
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......@@ -270,6 +254,22 @@
0000
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0210
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0100
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0100
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0044
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0044
1000
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1000
0000
0000
0000
......
io.pcf
+ 44
− 44
View file @ cfb8f85e
# For the iCESugar Board (iCE40UP5K-QFN48)
set_io LED_G 41
set_io LED_R 40
set_io LED_B 39
set_io -nowarn LED_G 41
set_io -nowarn LED_R 40
set_io -nowarn LED_B 39
set_io SW[0] 18
set_io SW[1] 19
set_io SW[2] 20
set_io SW[3] 21
set_io -nowarn SW[0] 18
set_io -nowarn SW[1] 19
set_io -nowarn SW[2] 20
set_io -nowarn SW[3] 21
set_io clk 35
set_io RX 4
set_io TX 6
set_io -nowarn RX 4
set_io -nowarn TX 6
set_io USB_DP 10
set_io USB_DN 9
set_io USB_PULLUP 11
set_io -nowarn USB_DP 10
set_io -nowarn USB_DN 9
set_io -nowarn USB_PULLUP 11
# PMOD 1
set_io P1_1 10
set_io P1_2 6
set_io P1_3 3
set_io P1_4 48
set_io P1_9 47
set_io P1_10 2
set_io P1_11 4
set_io P1_12 9
set_io -nowarn P1_1 10
set_io -nowarn P1_2 6
set_io -nowarn P1_3 3
set_io -nowarn P1_4 48
set_io -nowarn P1_9 47
set_io -nowarn P1_10 2
set_io -nowarn P1_11 4
set_io -nowarn P1_12 9
# PMOD 2
set_io P2_1 46
set_io P2_2 44
set_io P2_3 42
set_io P2_4 37
set_io P2_9 36
set_io P2_10 38
set_io P2_11 43
set_io P2_12 45
set_io -nowarn P2_1 46
set_io -nowarn P2_2 44
set_io -nowarn P2_3 42
set_io -nowarn P2_4 37
set_io -nowarn P2_9 36
set_io -nowarn P2_10 38
set_io -nowarn P2_11 43
set_io -nowarn P2_12 45
# PMOD 3
set_io P3_1 34
set_io P3_2 31
set_io P3_3 27
set_io P3_4 25
set_io P3_9 23
set_io P3_10 26
set_io P3_11 28
set_io P3_12 32
set_io -nowarn P3_1 34
set_io -nowarn P3_2 31
set_io -nowarn P3_3 27
set_io -nowarn P3_4 25
set_io -nowarn P3_9 23
set_io -nowarn P3_10 26
set_io -nowarn P3_11 28
set_io -nowarn P3_12 32
# PMOD 4
set_io P4_1 21
set_io P4_2 20
set_io P4_3 19
set_io P4_4 18
set_io -nowarn P4_1 21
set_io -nowarn P4_2 20
set_io -nowarn P4_3 19
set_io -nowarn P4_4 18
#spi
set_io SPI_SS 16
set_io SPI_SCK 15
set_io SPI_MOSI 17
set_io SPI_MISO 14
set_io -nowarn SPI_SS 16
set_io -nowarn SPI_SCK 15
set_io -nowarn SPI_MOSI 17
set_io -nowarn SPI_MISO 14
ram.mem 0 → 100644
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ram.v
+ 6
− 2
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......@@ -27,7 +27,7 @@ module ram(
.enHi(1'b0),
.enLo(1'b0));
assign busOut = enRam ? ramMemory[{currentMarHi,currentMarLo}] : 0;
assign busOut = enRam ? ramMemory[{currentMarHi,currentMarLo}] : 16'b0;
always @(posedge clk)
begin
......@@ -36,7 +36,11 @@ module ram(
end
end
reg [7:0] ramMemory [0:10];
reg [7:0] ramMemory [0:200];
initial begin
$readmemh("ram.mem", ramMemory);
end
......
top.json
+ 1739
− 1174
View file @ cfb8f85e
This diff is collapsed.
top.v
+ 118
− 242
View file @ cfb8f85e
......@@ -6,98 +6,107 @@
`include "alu.v"
module top(input [3:0] SW, output LED_R, output LED_G, output LED_B, input P3_10, input clk,
output P1_1, output P1_2, output P1_3, output P1_4, output P1_9, output P1_10, output P1_11, output P1_12);
reg clr = 1;
module top(
input [3:0] SW,
input P3_10,clk,
output LED_R, LED_G, LED_B, P1_1, P1_2, P1_3, P1_4, P1_9, P1_10, P1_11, P1_12
);
//debug output
assign LED_R = ~sClk;
assign LED_G = ~clr;
assign LED_B = ~hlt;
always @(negedge sClk)begin
clr <= 0;
end
assign P1_12 = bus_out[0]; //LSB
assign P1_1 = bus_out[1];
assign P1_11 = bus_out[2];
assign P1_2 = bus_out[3];
assign P1_10 = bus_out[4];
assign P1_3 = bus_out[5];
assign P1_9 = bus_out[6];
assign P1_4 = bus_out[7]; //MSB
reg clr = 1;
wire hlt;
reg sClk = 0;
`ifndef SYNTHESIS
always #1 sClk = ~sClk;
`endif
wire [15:0] bus_in_1;
wire [15:0] bus_in_3;
wire [15:0] bus_in_4;
wire [15:0] bus_in_5;
wire [15:0] bus_in_6;
reg [15:0] bus_in_2 = 0;
wire [15:0] bus_in_zReg;
wire [15:0] bus_in_ram;
wire [15:0] bus_in_pc;
wire [15:0] bus_in_instReg;
wire [15:0] bus_in_alu;
reg [15:0] bus_in_aux = 0;
// wor [15:0] altBus; alternative bus
wire [15:0] bus_out;
assign bus_out = bus_in_1 | bus_in_2 | bus_in_3 | bus_in_4 | bus_in_5 | bus_in_6;
assign bus_out = bus_in_zReg | bus_in_aux | bus_in_ram | bus_in_pc | bus_in_instReg | bus_in_alu;
assign LED_R = sClk;
reg [18:0] clock_div;
// reg sClk;
reg hlt = 0;
reg tmp =0;
reg one =1;
assign P1_12 = bus_out[0]; //LSB
assign P1_1 = bus_out[1];
assign P1_11 = bus_out[2];
assign P1_2 = bus_out[3];
assign P1_10 = bus_out[4];
assign P1_3 = bus_out[5];
assign P1_9 = bus_out[6];
assign P1_4 = bus_out[7]; //MSB
always @(posedge clk)
begin
// /* generate 9600 Hz clock */
cntr_9600 <= cntr_9600 + 1;
if (cntr_9600 == period_9600) begin
clk_9600 <= ~clk_9600;
cntr_9600 <= 32'b0;
end
//generate 1 Hz clock
cntr_1 <= cntr_1 + 1;
if (cntr_1 == period_1) begin
clk_1 <= ~clk_1;
cntr_1 <= 32'b0;
end
// Slow clock gen
clock_div <= clock_div + 1;
if(clock_div == 0 & ~hlt) begin
sClk <= ~sClk;
end
end
// reg [7:0] tmpbyte;
// assign tmpbyte = (clock_div[7:0] & 8'b00001111) | 8'b00110000 ;
// dff #(.WIDTH(8)) ff1(.d(tmpbyte), .q(tmpout), .clr(clr), .clk(P3_10));
`ifndef SYNTHESIS
always @(posedge hlt) begin
#2 $finish;
end
`endif
register zReg (.clk(sClk),.clr(clr),.in(bus_out),.out(bus_in_1),.wrHi(wrZhi),.wrLo(wrZlo),.enHi(enZhi),.enLo(enZlo));
register zReg (.clk(sClk),.clr(clr),.in(bus_out),.out(bus_in_zReg),.wrHi(wrZhi),.wrLo(wrZlo),.enHi(enZhi),.enLo(enZlo));
ram workingRam(.clk(sClk), .clr(clr), .busIn(bus_out), .busOut(bus_in_3), .wrMarHi(wrMarHi), .wrMarLo(wrMarLo), .wrRam(wrRam), .enRam(enRam));
ram workingRam(.clk(sClk), .clr(clr), .busIn(bus_out), .busOut(bus_in_ram), .wrMarHi(wrMarHi), .wrMarLo(wrMarLo), .wrRam(wrRam), .enRam(enRam));
pc programCounter(.inc(incPc), .clk(sClk), .enPc(enPc), .wrPc(wrPc), .clr(clr), .busIn(bus_out), .busOut(bus_in_4) );
pc programCounter(.inc(incPc), .clk(sClk), .enPc(enPc), .wrPc(wrPc), .clr(clr), .busIn(bus_out), .busOut(bus_in_pc) );
reg [5:0] stateCounter = 0;
always @ (negedge sClk or posedge clr) begin
if (clr) begin
always @ (negedge sClk) begin
if (clr | rstState) begin
stateCounter <= 0;
end else begin
stateCounter <= stateCounter + 1;
end
clr <= 0;
end
// always @ (posedge clk) begin
// if (rstState) begin
// stateCounter <= 0;
// end
// end
wire carryFlag;
wire zeroFlag;
wire [14:0]controlWord = {currentOp[6:0],stateCounter,zeroFlag,carryFlag};
// wire [7:0]controlWord = {stateCounter};
wire [15:0]controlLines;
......@@ -108,20 +117,32 @@ module top(input [3:0] SW, output LED_R, output LED_G, output LED_B, input P3_10
wire wrA = controlLines[0];
wire wrB = controlLines[1];
wire enSub = controlLines[2];
wire enSub = controlLines[3]; //
wire enAdd = controlLines[3];
wire wrZlo = controlLines[4];
wire wrZlo = controlLines[5]; //
wire wrZhi = controlLines[5];
wire enZlo = controlLines[6];
wire enZlo = controlLines[7]; //
wire enZhi = controlLines[7];
wire incPc = controlLines[8];
wire enPc = controlLines[9];
wire wrPc = controlLines[10];
wire rstState = controlLines[11];
wire wrMarHi = controlLines[12];
wire wrMarLo = controlLines[13];
wire wrRam = controlLines[14];
wire enRam = controlLines[15];
// wire wrMarHi = controlLines[12];
// wire wrMarLo = controlLines[13];
// wire wrRam = controlLines[14];
// wire enRam = controlLines[15];
wire wrMarHi = controlLines[4];
wire wrMarLo = controlLines[4];
reg wrRam = 1'b0;
wire enRam = controlLines[6];
wire wrInst = controlLines[2];
reg enInst = 0;
assign hlt = controlLines[12];
// wire wrMarLo = controlLines[13];
// wire wrRam = controlLines[14];
// wire enRam = controlLines[15];
reg wrFlags = 0;
// reg wrA = 0;
// reg wrB = 0;
......@@ -140,231 +161,86 @@ module top(input [3:0] SW, output LED_R, output LED_G, output LED_B, input P3_10
// reg wrRam = 0;
// reg enRam = 0;
reg wrInst = 0;
reg enInst = 0;
wire [7:0]currentOp;
register instReg (.clk(sClk),
.clr(clr),
.in(bus_out),
.out(bus_in_5),
.wrHi(wrInst),
.wrLo(wrInst),
.enHi(1'b0),
.enLo(enInst),
.currentLo(currentOp)
);
register instReg (
.clk(sClk),
.clr(clr),
.in(bus_out),
.out(bus_in_instReg),
.wrHi(wrInst),
.wrLo(wrInst),
.enHi(1'b0),
.enLo(enInst),
.currentLo(currentOp)
);
alu alu(
.clk(sClk),
.wrA(wrA),
.wrB(wrB),
.enAdd(enAdd),
.enSub(enSub),
.clr(clr),
.busIn(bus_out),
.busOut(bus_in_6),
.wrFlags(wrFlags),
.carryFlag(carryFlag),
.zeroFlag(zeroFlag)
.clk(sClk),
.wrA(wrA),
.wrB(wrB),
.enAdd(enAdd),
.enSub(enSub),
.clr(clr),
.busIn(bus_out),
.busOut(bus_in_alu),
.wrFlags(wrFlags),
.carryFlag(carryFlag),
.zeroFlag(zeroFlag)
);
initial begin
$readmemh("control.mem", controlMemory);
`ifndef SYNTHESIS
$dumpfile("wave.vcd");
$dumpvars;
`ifndef SYNTHESIS
#300 $finish;
#3000 $finish;
`endif
// #2 clr = 1;
// #2 clr = 0;
// reg test
// #2 bus_in_2 = 255;
// #2 wrZlo = 1;
// #2 wrZlo = 0;
// #2 bus_in_2 = 8;
// #2 wrZhi = 1;
// #2 wrZhi = 0;
// #2 bus_in_2 = 0;
// #2 enZhi = 1;
// #2 wrMarLo = 1;
// #2 enZhi = 0;
// #2 enZlo = 1;
// #2 enZhi = 1;
//ram test
// #2 clr = 1;
// #2 clr = 0;
// #2 bus_in_2 = 8;
// #2 wrRam = 1;
// #2 wrRam = 0;
// #2 bus_in_2 = 0;
// #2 enRam = 1;
// #2 enRam = 0;
// #2 bus_in_2 = 5;
// #2 wrMarLo = 1;
// #2 wrMarLo = 0;
// #2 bus_in_2 = 0;
// #2 wrRam = 1;
// #2 wrRam = 0;
// #2 enRam = 1;
// #2 enRam = 0;
// #2 wrInst=1;
// #2 bus_in_2 = 5;
// #2 wrA =1;
// #2 wrA =0;
// #2 bus_in_2 = 2;
// #2 wrB =1;
// #2 wrB =0;
// #2 bus_in_2 = 0;
// #2 enAdd = 1;
// #2 enAdd = 0;
// #2 enSub = 1;
// #20 $finish;
end
// reg [7:0] comp1;
// reg [7:0] comp2;
// assign bus_in_1[0] = SW[0];
// assign bus_in_1[1] = SW[1];
// assign bus_in_1[2] = SW[2];
// assign bus_in_1[7:3] = comp1[7:3];
// assign bus_in_2[0] = SW[3];
// assign bus_in_2[7:1] = comp2[7:1];
// assign LED_R = ~bus_out[0];
// assign LED_G = ~bus_out[1];
// assign LED_B = ~bus_out[2];
// assign hlt = SW[0];
// assign clr = SW[1];
// // initial begin
// // comp1 = 0;
// // comp2 = 0;
// // end
// always @(posedge clk)
// begin
// // Slow clock gen
// clock_div <= clock_div + 1;
// if(clock_div == 0 & ~hlt) begin
// sClk <= ~sClk;
// end
// end
// // assign LED_G = sClk;
// // assign sClk = SW[3];
// /* 9600 Hz clock generation (from 12 MHz) */
// reg clk_9600 = 0;
// reg [31:0] cntr_9600 = 32'b0;
// 9600 Hz clock generation (from 12 MHz)
reg clk_9600 = 0;
reg [31:0] cntr_9600 = 32'b0;
parameter period_9600 = 625;
// parameter period_9600 = 625;
// // parameter period_9600 = 625;
// /* 1 Hz clock generation (from 12 MHz) */
// reg clk_1 = 0;
// reg [31:0] cntr_1 = 32'b0;
// parameter period_1 = 6000000;
// // Note: could also use "0" or "9" below, but I wanted to
// // be clear about what the actual binary value is.
// parameter ASCII_0 = 8'd48;
// parameter ASCII_9 = 8'd122;
// 1 Hz clock generation (from 12 MHz)
reg clk_1 = 0;
reg [31:0] cntr_1 = 32'b0;
parameter period_1 = 6000000;
// /* UART registers */
// reg [7:0] uart_txbyte = ASCII_0;
// reg uart_send = 1'b1;
// wire uart_txed;
parameter ASCII_0 = 8'd48;
parameter ASCII_9 = 8'd122;
// /* LED register */
// reg ledval = 0;
// UART registers
reg [7:0] uart_txbyte = ASCII_0;
reg uart_send = 1'b1;
wire uart_txed;
// reg [7:0] test_memory [0:200];
// initial begin
// // test_memory[0] = 8'd48;
// // test_memory[1] = 8'd49;
// // test_memory[2] = 8'd50;
// $readmemh("text.mem", test_memory);
// end
// uart_tx_8n1 transmitter (
// // 9600 baud rate clock
// .clk (clk_9600),
// // .clk (clk_9600),
// .clk (sClk),
// // byte to be transmitted
// // .txbyte (test_memory[pointer]),
// .txbyte (tmpout),
// .txbyte ("A"),
// // trigger a UART transmit on baud clock
// .senddata (1'b1),
// // input: tx is finished
// .txdone (uart_txed),
// // output UART tx pin
// .tx (TX),
// .tx (TX)
// );
// reg [5:0] pointer;
// /* Low speed clock generation */
// always @ (posedge clk) begin
// /* generate 9600 Hz clock */
// cntr_9600 <= cntr_9600 + 1;
// if (cntr_9600 == period_9600) begin
// clk_9600 <= ~clk_9600;
// cntr_9600 <= 32'b0;
// end
// /* generate 1 Hz clock */
// cntr_1 <= cntr_1 + 1;
// if (cntr_1 == period_1) begin
// clk_1 <= ~clk_1;
// cntr_1 <= 32'b0;
// end
// end
// /* Increment ASCII digit and blink LED */
// always @ (posedge uart_txed ) begin
// pointer <= pointer +1;
// // if (uart_txbyte == ASCII_9) begin
// // uart_txbyte <= ASCII_0;
// // end else begin
// // uart_txbyte <= uart_txbyte + 1;
// uart_txbyte <= tmpout;
// // end
// end
endmodule
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